Intel Server Management (ISM) Installation and User's Guide, Version 5.5.5 - HP Carrier-Grade Server cc3310

Intel Server Management (ISM) Installation and User's Guide
Client SSU (CSSU) Details
Figure 4-3 Fan Status Display with all Fan Installed
Memory Displays
Memory and memory error correction are represented by the following items:
• Memory Devices
• Memory Arrays
For systems that support Error Correction Code (ECC) memory, PIC reports memory status information for
memory arrays and individual memory devices. When you highlight a device or array in the navigation
pane, the presentation pane displays a variety of information about the selected device(s). The Sensor Status
tab lists details about memory errors. The Sensor Information tab lists details about the memory type and
error handling. When you select a memory array, you can configure alert actions to be taken on the Alert
Actions tab. There is also a System Inventory tab for memory arrays that lists hardware details.
ECC memory subsystems can detect and report both single-bit errors and multiple-bit errors, as described in
the following sections.
Single-Bit Error (SBE) Handling
If a single bit error occurs, the system generates a System Management Interrupt (SMI) that allows the
BIOS to log information about the error in the System Event Log (SEL). This information identifies the
exact memory device in which the error occurred. Because this condition is recoverable, BIOS returns the
system to normal operation after logging the error.
This error is indicated in the health branch of PIC as a noncritical condition, the requested event actions are
carried out, and PIC:
• Increments the noncritical error count on the Sensor Settings tab
• Sets the Memory Device Error Type to SBE on the Sensor Information tab for the Memory Device