User Service Guide, Second Edition - HP Integrity BL60p Server Blade

Troubleshooting
CPU/Memory/SBA
Chapter 5
87
It is the processor’s cache controller logic that issues cache line fetches from PDH/physical shared memory,
when a requested cache line is not within its instruction or data cache. Cache line fetches are transferred over
the McKinley bus, between processors and PDH/physical shared memory.
Customer Messaging Policy
No diagnostic messages are reported for single-bit errors, that are corrected in both instruction and data
caches, during corrected machine check (CMC) events to any physical processor core. Diagnostic messages are
reported for CMC events, when thresholds are exceeded for single-bit errors; fatal processor errors cause
global/local MCA events.
Troubleshooting Blade Memory
The memory controller logic in the Zx1 chip supports two physical ranks, that hold 2 memory DIMMs each.
Memory DIMMs installed in groups of four are known as a quad, and must be the same size and
configuration.
Memory DIMM Load Order
For a minimally loaded server, two equal-size memory DIMMs must be installed into rank 0’s slots 0A and 0B.
The next two DIMMs are loaded into rank 1’s slots 1A and 1B.
Memory Subsystem Behaviors
All server blades with Zx1 chips provide error detection and correction of all memory DIMM single-bit errors,
and error detection of most multi-bit errors within a 128 byte cache line.
The Zx1 chip provides memory DIMM error correction for up to 4 bytes of a 128 byte cache line, during cache
line misses initiated by processor cache controllers, and by Direct Memory Access (DMA) operations, initiated
by I/O devices. This feature is called chip sparing, as 1 of 72 total DRAMs in any memory quad can fail
without any loss of server blade performance.
Customer Messaging Policy
PDT logs for all double bit errors are permanent; single bit errors are initially logged as transient errors. If
the server logs 2 single bit errors within 24 hours, then it upgrades them to permanent status in the PDT.
Troubleshooting Blade SBA
Each server blade’s system bus adapter (SBA) supports core I/O, SCSI, LAN, and FibreChannel functions.
The System Bus Adapter (SBA) logic within the Zx1 chip of a server blade uses 6 of 8 ropes to support 4 Lower
Bus Adapter (LBA) chips. Each LBA chip interfaces with the SBA in the Zx1 chip, through one or multiple
rope connections, as follows:
• One LBA chip uses a single rope connection (used by core I/O) to support a single 32-bit PCI bus running
@ 33 MHz;
• One LBA chip use a single-rope connection (used by SCSI controller) to support one 64-bit PCI-X bus
running @ 66 MHz;
• Two LBA chips use a dual rope connection (used by LAN and FibreChannel controllers) to support
individual 64-bit PCI-X buses running @ 133 MHz;