C/C++ Programmer's Guide (G06.27+, H06.08+, J06.03+)

22 Handling TNS Data Alignment
Programs compiled with the TNS instruction set must follow the even-byte data alignment rules of
TNS compilers. Certain violations of these programming rules might lead to run-time errors. This
section describes these violations and explains how to avoid them and how to diagnose them at
run time.
On TNS systems, a word is 16 bits. The TNS instruction set includes data access instructions that
expect 32-bit byte addresses that must be even-byte aligned (that is, aligned 0 modulo 2) for correct
operation. In TNS mode and Accelerator mode, addresses that are odd-byte aligned (that is,
aligned 1 modulo 2) are called misaligned. TNS processors consistently “round down” misaligned
addresses (that is, they ignore the low-order bit).
TNS/R and TNS/E processors handle misaligned addresses of TNS programs inconsistently,
rounding down some but not others and behaving differently in TNS mode and accelerated mode.
Compilers cannot catch misaligned addresses that are computed at run time.
The behavior of TNS programs with misaligned addresses on TNS/R or TNS/E processors is almost
impossible to predict. If you are not sure that your program has only aligned addresses, you can
use the tracing facility to detect whether programs are using misaligned pointers, and if so, where.
You should then change the programs to avoid misalignment.
The round-downs occur only in TNS-compiled C and C++ programs, native C or C++ programs.
In native mode, misalignments can slow down a program, but they cannot cause errors.
The data misalignment issue might affect programs that use these HP products. If you use these
products, see the appropriate manual or addendum:
Manual or AddendumNumberProduct
This manualT9255TNS C
This manualT9541TNS C++
This manualT8629G-series TNS c89
This manualT8164TNS/E c89
This manualT9577TNS/E CCOMP
This manualT9225TNS/E CPPCOMP
This manualT8164TNS/R c89
This manualT9577TNS/R NMC
This manualT9225TNS/R NMCPLUS
Accelerator ManualT9276Accelerator
COBOL Manual for TNS and TNS/RT9257TNS COBOL85 and OSS cobol
pTAL Reference ManualT9248TNS/E EpTAL
pTAL Reference ManualT9248TNS/R pTAL
TAL Programmer’s Guide Data
Alignment Addendum
T9250TNS TAL
Misalignment Tracing Facility
The misalignment tracing facility is enabled or disabled on a system-wide basis (that is, for all
processors in the node). By default, it is enabled (set to ON). It can be disabled (set to OFF) only
by the persons who configure the system, using the Subsystem Control Facility (SCF) attribute
MISALIGNLOG. Instructions are in the SCF Reference Manual for the Kernel Subsystem.
Misalignment Tracing Facility 383