H06.03 Software Installation and Upgrade Guide

Overview of Installing the H06.03 RVU
H06.03 Software Installation and Upgrade Guide—540066-002
1-12
Managing Firmware in a Processor Complex (Blade
Complex)
For more information on the NonStop advanced architecture (NSAA), see the NonStop
NS-Series Planning Guide.
Updating processor boot code is part of the Halted State Services (HSS) firmware,
which consists of HSS Main, Primitive State code (pState), SCSI firmware (ISP1040),
bootstrap (Diskboot), Baseboard Management Controller (BMC) firmware, and
PAL/SAL firmware (IPF Firmware.) HSS provides interfaces compatible with existing
NonStop interfaces for RELOAD and RCVDUMP.
You use OSM and the new Processor Complex Firmware Update guided procedure to
update your HSS firmware. The OSM Service Connection indicates whether the
firmware is downrev and must be updated. All NonStop NS-server firmware files are
placed in SYSnn.
Term Description
Processor element
(PE)
A single Integrity NonStop NS-series microprocessor with its
associated memory.
Slice (Blade) element Two or four PEs contained within a single processor (blade) complex
enclosure.
Logical processor One or more PEs from each slice (blade element) executing a single
instruction stream. A duplex processor (DMR) has two PEs forming a
logical processor. A triplex processor (TMR) has three PEs. For
example:
Logical
synchronization unit
(LSU)
The combination of the LSU logic board and the LSU optics adapter.
An LSU serves one logical processor.
Processor (Blade)
Complex
Two slices or blade elements (DMR) or three slices or blade elements
(TMR). An Integrity NonStop NS-series server includes up to four
processor (blade) complexes.
NSBE
(Slice) A
P
E
A
0
P
E
A
1
P
E
A
3
NSBE
(Slice) B
P
E
B
0
P
E
B
1
P
E
B
3
NSBE
(Slice) C
P
E
C
0
P
E
C
1
P
E
C
3
TMR
Logical Processor
P
E
A
2
P
E
B
2
P
E
C
2
Blade Element
(Slice)
VST727.vsd