ld Manual

Glossary
ld Manual529650.001
Glossary-5
RISC instructions
RISC instructions. Register-oriented 32-bit machine instructions that are directly executed
on TNS/R processors. RISC instructions execute only on TNS/R systems, not on TNS
systems.
Accelerator-generated RISC instructions are produced by accelerating TNS object
code. Native-compiled RISC instructions are produced by compiling source code with a
TNS/R native compiler.
RISC word. An instruction-set-defined unit of memory. A RISC word is 4 bytes (32 bits)
wide, beginning on any 4-byte boundary in memory.
shared code. See PIC (position-independent code).
shared run-time library (SRL). A loadfile supplied by HP that the operating system links to
a program file at run time. See also TNS/R native shared run-time library (TNS/R
native SRL).
simple name. A Guardian file identifier or an OSS path name without any directory
components.
SRL. See shared run-time library (SRL).
startup directory. Your current working directory at the time you invoked the utility.
symbols information. The tables in an object file that contain information for linking object
files and symbolic debugging programs using the Visual Inspect debugger or the
Inspect symbolic debugger.
system library. A logically distinct part of the operating system that consists of user-callable
library procedures and OS procedures.
TAL. See Transaction Application Language (TAL).
TNS. Fault-tolerant HP computers that support the HP NonStop operating system and that
are based on complex instruction-set computing (CISC) technology. TNS processors
implement the TNS instruction set. Compare to TNS/R.
TNS/R. HP computers that support the NonStop OS and that are based on reduced
instruction-set computing (RISC) technology. TNS/R processors implement the RISC
instruction set and are upwardly compatible with the TNS system-level architecture.
Compare to TNS.
TNS/R native C compiler. The HP C compiler that generates TNS/R object files.
TNS/R native mode. The operational environment in which native-compiled RISC
instructions execute.