NonStop NS-Series Planning Guide (H06.03+)

Introduction to Integrity NonStop NS-Series Systems
HP Integrity NonStop NS-Series Planning Guide—529567-004
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NonStop Advanced Architecture
However, contemporary high-speed microprocessors make lock-step processing no
longer practical because of:
•
Variable frequency processor clocks with multiple clock domains
•
Higher transient error rates than in earlier, simpler microprocessor designs
•
Chips with multiple processor cores
NonStop Advanced Architecture
Integrity NonStop NS-series systems employ a unique method for achieving fault
tolerance in a clustered processor environment: the modular NonStop advanced
architecture (NSAA). NSAA utilizes standard Intel® Itanium® microprocessors, without
cycle-by-cycle lock-stepping. Instead, two or three microprocessors run the same
instruction stream concurrently in a loose lockstep process. In loose lockstep:
•
Each microprocessor runs at its own clock rate.
•
Results of each command execution are compared on processor output to the
ServerNet fabric.
•
Error recovery and minor indeterminate processing results from one
microprocessor do not cause output comparison errors.
If the output of one microprocessor is incorrect, it is discarded, and its source
microprocessor is taken offline for error handling and correction. The remaining
functional hardware continues normal operation until the errant microprocessor is
again operational. At that time, all microprocessors are synchronized and then proceed
with executing instructions.
NSAA and Integrity NonStop NS-series systems use modular hardware implemented in
enclosures with fiber-optic cabling between these enclosures. These enclosures reside
in a specialized 19-inch computer equipment racks.