NonStop NS-Series Planning Guide (H06.03+)

Introduction to Integrity NonStop NS-Series Systems
HP Integrity NonStop NS-Series Planning Guide—529567-004
1-6
Duplex Processor
communications redundancy in case one of the fabrics fails. For description of the LSU
functions, see Processor Synchronization and Rendezvous on page 1-8.
A duplex processor includes these elements:
VST303.vsd
LSU
Enclosure
Slice B
Slice A
Slice (4-way
SMP server
includes PEs
A0, A1, A2, A3)
PE
A2
PE
B2
PE
A3
PE
B3
ServerNet Links to
Processor Switch
Slice
Optic
Cables
Logical Processor 0
(includes PEs A0, B0)
Processor Element A0
(slice A, logical processor 0)
23
LSU 0
(for PEs A0, B0)
Processor
Complex 0
LSU 2
Vote
Logic
A B C
Optic
I/O
X Y
LSU 3
Vote
Logic
A B C
Optic
I/O
X Y
PE
A1
PE
B1
1
LSU 1
Vote
Logic
A B C
Optic
I/O
X Y
PE
A0
0
LSU 0
Vote
Logic
A B C
Optic
I/O
X Y
PE
B0