NonStop NS-Series Planning Guide (H06.03+)

Introduction to Integrity NonStop NS-Series Systems
HP Integrity NonStop NS-Series Planning Guide—529567-004
1-7
Triplex Processor
Triplex Processor
The TMR or triplex processor uses three slices, A, B, and C. As with the duplex
processor, the slice optic cables connect the PEs to the LSUs with these LSUs then
connecting to the two independent ServerNet fabrics. Dual ServerNet fabrics create
communications redundancy in case one of the fabrics fails. For a description of the
LSU functions, see Processor Synchronization and Rendezvous on page 1-8.
A triplex processor includes these elements:
In a TMR or triplex processor, each LSU has inputs from three PEs. As with the duplex
processor, the LSU keeps the three PEs in loose lockstep. Triplex processor provides
fault tolerance upon failure of a PE by comparing the output from the three slices to
determine which one is errant. This method eliminates the question of which output is
valid when two outputs disagree in a duplex system.
VST310.vsd
Slice B
Slice A
Slice C
Slice (4-way
SMP server
includes PEs
A0, A1, A2, A3)
PE
A2
PE
B2
PE
C2
PE
A3
PE
B3
PE
C3
Slice
Optic
Cables
Logical Processor 0
(includes PEs A0, B0, C0
Processor Element A0
(slice A, logical processor 0)
23
PE
A0
PE
B0
PE
C0
0
PE
A1
PE
B1
PE
C1
1
LSU
Enclosure
ServerNet Links to
Processor Switch
LSU 0
(for PEs A0, B0, C0)
Processor
Complex 0
LSU 2
Vote
Logic
A B C
Optic
I/O
X Y
LSU 3
Vote
Logic
A B C
Optic
I/O
X Y
LSU 1
Vote
Logic
A B C
Optic
I/O
X Y
LSU 0
Vote
Logic
A B C
Optic
I/O
X Y