NonStop NS-Series Planning Guide (H06.03+)
System Configurations
HP Integrity NonStop NS-Series Planning Guide—529567-004
4-13
Processor Switches to IOAM Enclosures
ServerNet cables connected to the p-switch PICs in slots 10 through 13 come from the
LSUs and processors, with the cable connection to these PICs determining the
processor identification. (See LSUs to Processor Switches and Processor IDs on
page 4-8.) Cables connected to the PICs in slots 4 though 9 connect to one or more
IOAM enclosures or to NonStop S-series I/O enclosures equipped with IOMF 2 CRUs.
This illustration shows the connections to the PICs in a fully populated p-switch:
Unlike the fixed hardware I/O configurations and topologies in NonStop S-series
systems, I/O configurations in Integrity NonStop NS-series system are flexible with few
restrictions. Those few restrictions are to prevent I/O configurations that compromise
fault tolerance or high availability, especially with disk storage as outlined in Fibre
Channel Device Configuration Restrictions on page 4-22.
Processor Switches to IOAM Enclosures
Each p-switch (for the X or Y ServerNet fabric) has up to six I/O PICs. One I/O PIC is
required for each IOAM enclosure in the system, allowing up six IOAM enclosures in
the system. Four ServerNet cables, called a fat pipe connection, connect each of the
four ports of an I/O PIC in the X and Y ServerNet p-switches to the corresponding ports
on one of the ServerNet switch boards in the IOAM enclosure.
These restrictions apply to connecting the p-switches to the IOAMs:
•
The same PIC number in the X and Y p-switch must be used, such as PIC 4 as
shown in the illustration on the next page.
•
Each port on the p-switch PIC must connect to the same numbered port on the
IOAM ServerNet switch board (port 1 to port 1, port 2 to port 2, and so forth).
•
Connections to an IOAM enclosure cannot co-exist on the same p-switch PIC with
connections to a NonStop S-series I/O enclosure.
Processor
Switch
(rear view)
VST513.vsd
I/O PICs
(slots 4 - 9 to IOAM or S-series I/O enclosures)
Processor PICs
(slots 10 - 13 to LSUs)
Maintenance
PIC (slot 1)
Cluster PIC
(slot 2)
Crosslink PIC
(slot 3)
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
EFT