NonStop NS-Series Planning Guide (H06.04+)
Table Of Contents
- What’s New in This Manual
- About This Manual
- 1 System Hardware Overview
- 2 Installation Facility Guidelines
- 3 System Installation Specifications
- 4 Integrity NonStop NSSeries System Description
- NonStop System Primer
- NonStop Advanced Architecture
- NonStop Blade Complex
- Processor Element
- Duplex Processor
- Triplex Processor
- Processor Synchronization and Rendezvous
- Memory Reintegration
- Failure Recovery for Duplex Processor
- Failure Recovery for Triplex Processor
- ServerNet Fabric I/O
- System Architecture
- Modular Hardware
- NonStop S-Series I/O Hardware
- System Models
- Default Startup Characteristics
- Migration Considerations
- System Installation Document Packet
- 5 Modular System Hardware
- Modular Hardware Components
- Cabinets
- AC Power PDUs
- Modular Cabinet PDU Keepout Panel
- NonStop Blade Element
- Logical Synchronization Unit (LSU)
- LSU Indicator LEDs
- Processor Switch
- P-Switch Indicator LEDs
- Processor Numbering
- I/O Adapter Module (IOAM) Enclosure and I/O Adapters
- Fibre Channel Disk Module
- Tape Drive and Interface Hardware
- Maintenance Switch (Ethernet)
- Optional UPS and ERM
- System Console
- Enterprise Storage System
- Component Location and Identification
- NonStop S-Series I/O Enclosures
- Modular Hardware Components
- 6 System Configuration Guidelines
- Enclosure Locations in Cabinets
- Internal ServerNet Interconnect Cabling
- Cable Labeling
- Cable Management System
- Internal Interconnect Cables
- Dedicated Service LAN Cables
- Cable Length Restrictions
- Internal Cable Part Numbers
- NonStop Blade Elements to LSUs
- NonStop Blade Element to NonStop Blade Element
- LSUs to Processor Switches and Processor IDs
- Processor Switch ServerNet Connections
- Processor Switches to IOAM Enclosures
- FCSA to Fibre Channel Disk Modules
- FCSA to Tape Devices
- P-Switch to NonStop S-Series I/O Enclosure Cabling
- IOAM Enclosure and Disk Storage Considerations
- Fibre Channel Devices
- G4SAs to Networks
- Default Naming Conventions
- PDU Strapping Configurations
- 7 Example Configurations
- A Cables
- B Control, Configuration, and Maintenance Tools
- Support and Service Library
- System Console
- Maintenance Architecture
- Dedicated Service LAN
- IP Addresses
- Ethernet Cables
- SWAN Concentrator Restriction
- System-Up Dedicated Service LAN
- Dedicated Service LAN Links With One IOAM Enclosure
- Dedicated Service LAN Links to Two IOAM Enclosures
- Dedicated Service LAN Links With IOAM Enclosure and NonStop SSeries I/O Enclosure
- Dedicated Service LAN Links With NonStop S-Series I/O Enclosure
- Initial Configuration for a Dedicated Service LAN
- Operating Configurations for Dedicated Service LANs
- OSM
- System-Down OSM Low-Level Link
- AC Power Monitoring
- AC Power-Fail States
- C Guide to Integrity NonStop NSSeries Server Manuals
- Safety and Compliance
- Index
Integrity NonStop NS-Series System Description
HP Integrity NonStop NS-Series Planning Guide—529567-005
4-5
Duplex Processor
•
I/O interface with maintenance logic shared with the other PEs in the NonStop
Blade Element
•
Interface for fiber-optic I/O communications with the corresponding LSU
•
Memory reintegration logic and fiber-optic links shared with the other PEs in the
NonStop Blade Element and used for memory rendezvous between the NonStop
Blade Elements
The diagram provides an overview of the processor element architecture:
Duplex Processor
The DMR or duplex processor uses two NonStop Blade Elements, A and B, both with
two or four microprocessors. Fiber optic cables from eash NonStop Blade Element
connect the PEs to the LSUs. These LSUs then connect to two independent ServerNet
fabrics. These two connections create communications redundancy in case one of the
fabrics fails. For a description of the LSU functions, see Processor Synchronization
and Rendezvous on page 4-7.
VST747.vsd
I/O and Memory
Controller
Fiber-Optic
I/O 0-3
DIMM Main
Memory
Memory
Copy
Memory Reintegration
to Other NSBEs
Fiber Optic
Link to LSUs
Memory
Reintegration From
Other NSBEs
Microprocessor
0-3
Logic shared by all
microprocessors in
NSBE
Logic dedicated to
microprocessor
0, 1, 2, or 3