NonStop NS-Series Planning Guide (H06.04+)

Integrity NonStop NS-Series System Description
HP Integrity NonStop NS-Series Planning Guide—529567-005
4-7
Processor Synchronization and Rendezvous
A triplex processor includes these elements:
In a TMR or triplex processor, each LSU has inputs from three PEs. As with the duplex
processor, the LSU keeps the three PEs in loose lockstep. Triplex processor provides
fault tolerance upon failure of a PE by comparing the output from the three NonStop
Blade Elements to determine which one is errant. This method eliminates the question
of which output is valid when two outputs disagree in a duplex system.
Processor Synchronization and Rendezvous
Synchronization and rendezvous at the LSUs perform two main functions:
•
Keep the individual PEs in a logical processor in loose lock-step through a
technique called rendezvous. Rendezvous occurs to:
°
Periodically synchronize the PEs so they execute the same instruction at the
same time. Synchronization accommodates the slightly different clock speed
within each PE.
VST310.vsd
NSBE B
NSBE A
NSBE C
NSBE (4-way
SMP server
includes PEs
A0, A1, A2, A3)
PE
A2
PE
B2
PE
C2
PE
A3
PE
B3
PE
C3
Fiber
Optic
Cables
Logical Processor 0
(includes PEs A0, B0, C0
Processor Element A0
(NSBE A, logical processor 0)
23
PE
A0
PE
B0
PE
C0
0
PE
A1
PE
B1
PE
C1
1
LSU
Enclosure
ServerNet Links to
Processor Switch
LSU 0
(for PEs A0, B0, C0)
NonStop Blade
Complex 0
LSU 2
Vote
Logic
A B C
Optic
I/O
X Y
LSU 3
Vote
Logic
A B C
Optic
I/O
X Y
LSU 1
Vote
Logic
A B C
Optic
I/O
X Y
LSU 0
Vote
Logic
A B C
Optic
I/O
X Y