NonStop NS16000 Planning Guide (H06.08+)

Integrity NonStop NS16000 System Description
HP Integrity NonStop NS16000 Planning Guide—529567-009
4-5
Processor Element
Processor Element
Each of the two or four processor elements in a NonStop Blade Element includes:
•
A standard Intel Itanium microprocessor running at 1.6 GHz with a 6-MB cache
•
4, 8, or 16 GB of main memory partitioned from DDR SDRAM DIMMs
•
I/O interface with maintenance logic shared with the other PEs in the NonStop
Blade Element
•
Interface for fiber-optic I/O communications with the corresponding LSU
•
Memory reintegration logic and fiber-optic links shared with the other PEs in the
NonStop Blade Element and used for memory rendezvous between the NonStop
Blade Elements
This diagram provides an overview of the processor element architecture:
VST747.vsd
I/O and Memory
Controller
Fiber-Optic
I/O 0-3
DIMM Main
Memory
Memory
Copy
Memory Reintegration
to Other NSBEs
Fiber Optic
Link to LSUs
Memory
Reintegration From
Other NSBEs
Microprocessor
0-3
Logic shared by all
microprocessors in
NSBE
Logic dedicated to
microprocessor
0, 1, 2, or 3