NonStop Systems Introduction for H-Series RVUs

Integrity NonStop NS-Series Server Architecture
NonStop Systems Introduction for H-Series RVUs—540083-001
7-8
Dual Access Paths for I/O
The ServerNet interface, shown for each processor, serves to convert messages
coming from the message system into chains of ServerNet packets or, conversely, to
convert chains of ServerNet packets into messages for the message system.
ServerNet packets are the form in which messages travel from source to destination
through the ServerNet fabric.
The distance that messages need to travel can vary considerably, and likewise the
number of routers that need to be traversed can vary. For example, a message going
from processor 0 to processor 1 needs to go through only one router (either by way of
the X fabric or the Y fabric), whereas another message going to processor 2 needs to
go through four routers. The reason for the difference is that the two pairs of
processors are physically located in different enclosures (0 and 1 in one enclosure, 2
and 3 in another). There is a separate router for entry and exit to and from each
enclosure.
In Figure 7-5 on page 7-7, the two ServerNet fabrics have been separated in order to
show the ServerNet routers that are needed to interconnect these processors. Each
router is a multiple-port crossbar switch (actually an application-specific integrated
circuit, or ASIC) that can simultaneously connect any input port with any output port.
At first glance, this arrangement might seem like unnecessary data handling, and a bus
might seem more direct. However, all eight of the processor connections to the two
ServerNet fabrics can be simultaneously active, either sending or receiving a message.
In a bus interconnection, by contrast, each bus is exclusively tied up while one
transmission is in progress. The disparity becomes even greater when there are more
processors in the system; there remain only two buses, but an ever greater number of
available routers. Thus, overall throughput is far greater for a ServerNet architecture
than for a bus architecture.
Just as important, the intervening routers (2, 3, 6, and 7 in this example) provide
additional ServerNet ports that allow massive expandability for both processors and
I/O. The NonStop NS-Series Server Description Manual discusses the theoretical
expansion that is possible because of all the ServerNet ports that can be
interconnected. Implementing just a portion of the theoretical limits of ServerNet
expandability provides an overall bandwidth that bus architectures cannot approach.
Dual Access Paths for I/O
Applications obtain the data to be processed from I/O devices and send the results of
processing to I/O devices. The ServerNet hardware and device controllers coordinate
these data transfers between applications and devices. This arrangement is illustrated
in Figure 7-6 on page 7-9.