pTAL Reference Manual (H06.03+)

Glossary
HP pTAL Reference Manual—523746-005
Glossary-4
CPU
CPU. See central processing unit (CPU).
CRE. Common Run-Time Environment. Services that facilitate mixed-language programs.
data segment. A virtual memory segment holding data. Every process begins with its own
data segments for program global variables and runtime stacks (and for some libraries,
instance data). Additional data segments can be dynamically created.
DEFINE. An HP Tandem Advanced Command Language (TACL) command you can use to
specify a named set of attributes and values to pass to a process.
definition structure. A declaration that describes a structure layout and allocates storage
for the structure layout. Compare to referral structure and template structure.
direct addressing. Data access that requires only one memory reference and that is
relative to the base of the global, local, or sublocal area of the data space. Compare to
extended addressing.
DLL. See dynamic-link library (DLL).
doubleword. A 32-bit storage unit for the INT(32) or REAL data type.
dynamic-link library (DLL). A collection of procedures whose code and data can be loaded
and executed at any virtual memory address, with run-time resolution of links to and
from the main program and other independent libraries. The same DLL can be used by
more than one process. Each process gets its own copy of DLL static data.
entry point. An identifier by which a procedure can be called. The primary entry point is the
procedure identifier specified in the procedure declaration. Secondary entry points are
identifiers specified in entry-point declarations.
EPIC. See explicitly parallel instruction set computing (EPIC).
EpTAL compiler. The compiler that takes pTAL source code as input and generates either
TNS/R native object code or TNS/E native object code. Compare to pTAL compiler and
TAL compiler.
equivalenced variable. A declaration that associates an alternate identifier and description
with a location in a primary storage area.
executable object file. See loadfile.
explicitly parallel instruction set computing (EPIC). A processor architecture in which
the instruction stream encodes what can be done in parallel (so that the hardware
need not do this). Compare to complex instruction set computing (CISC) and reduced
instruction set computing (RISC).
expression. A sequence of operands and operators that, when evaluated, produces a
single value.