pTAL Reference Manual (H06.08+)

Glossary
HP pTAL Reference Manual—523746-006
Glossary-13
TNS accelerated mode
TNS accelerated mode. A TNS emulation environment on a TNS/R or TNS/E system in
which accelerated TNS object files are run. TNS instructions have been previously
translated into optimized sequences of MIPS or Intel® Itanium® instructions. TNS
accelerated mode runs much faster than TNS interpreted mode. Accelerated or
interpreted TNS object code cannot be mixed with or called by native mode object
code. See also TNS Object Code Accelerator (OCA). Compare to native mode.
TNS architecture. NonStop Series architecture. HP computers that are based on CISC
technology. TNS architecture implements the TNS instruction set.
TNS mode. The operational environment in which unaccelerated TNS instructions execute.
Compare to TNS accelerated mode and native mode.
TNS object code. The TNS instructions that result from processing program source code
with a TNS compiler. TNS object code executes on TNS, TNS/R, and TNS/E systems.
TNS Object Code Accelerator (OCA). A program optimization tool that processes a TNS
object file and produces an accelerated file for the TNS/E architecture. OCA augments
a TNS object file with equivalent Intel® Itanium® instructions. TNS object code that is
accelerated runs faster on TNS/E systems than TNS object code that is not
accelerated.
TNS/E architecture. NonStop Series/Itanium architecture. HP computers that are based on
Itanium technology. TNS/E architecture implements the Itanium instruction set
[explicitly parallel instruction set computing (EPIC)] and are upwardly compatible with
the TNS and TNS/R system-level architectures.
TNS/E native object code. The Intel®® Itanium® instructions that result from processing
program source code with a TNS/E native compiler. TNS/E native object code
executes only on TNS/E systems, not on TNS systems or TNS/R systems.
TNS/R architecture. NonStop Series/RISC architecture. HP computers that are based on
RISC technology. TNS/R architecture implements the RISC instruction set and are
upwardly compatible with the TNS system-level architecture.
TNS/R native object code. The MIPS RISC instructions that result from processing
program source code with a TNS/R native compiler. TNS/R native object code
executes only on TNS/R systems, not on TNS systems or TNS/E systems.
trap. A software interrupt that provides a way of handling certain events, such as detection
of a hardware (or software) fault, a timer expiration, or a lack of system resources. A
trap is often an indication of a run-time event that requires immediate attention. Most
such events preclude continuing the interrupted instruction stream. Traps are
generated for TNS Guardian processes. (TNS/R native Guardian processes receive
signals instead.) An Instruction Failure trap indicates that an instruction cannot execute
because the instruction or its data are invalid. Compare to signal.