H06.08 Software Installation and Upgrade Guide

Overview of Installing the H06.08 RVU
H06.08 Software Installation and Upgrade Guide—543573-001
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Managing Firmware in a NonStop Blade Complex
The following terms briefly describe the NonStop Blade Complex, which is composed
of two or three NonStop Blade Elements and their associated logical synchronization
units (LSUs):
For more information on the NonStop advanced architecture (NSAA), see the NonStop
NS-Series Planning Guide.
Updating processor boot code is part of the Halted State Services (HSS) firmware,
which consists of HSS Main, Primitive State code (pState), SCSI firmware (ISP1040),
bootstrap (Diskboot), Baseboard Management Controller (BMC) firmware, and
PAL/SAL firmware (IPF Firmware.) HSS provides interfaces compatible with existing
NonStop interfaces for RELOAD and RCVDUMP.
Term Description
Processor element
(PE)
A single Integrity NonStop NS-series microprocessor with its
associated memory.
NonStop Blade
element
Two or four PEs contained within a single processor (blade) complex
enclosure.
Logical processor One or more PEs from each NonStop Blade Element executing a
single instruction stream. A duplex processor (DMR) has two PEs
forming a logical processor. A triplex processor (TMR) has three
PEs. For example:
Logical
synchronization unit
(LSU)
The combination of the LSU logic board and the LSU optics adapter.
An LSU serves one logical processor.
Processor (Blade)
Complex
Two slices or Blade Elements (DMR) or three slices or Blade
Elements (TMR). An Integrity NonStop NS-series server includes up
to four processor (blade) complexes.
Processor Element
NSBE
(Slice) A
P
E
A
0
P
E
A
1
P
E
A
3
NSBE
(Slice) B
P
E
B
0
P
E
B
1
P
E
B
3
NSBE
(Slice) C
P
E
C
0
P
E
C
1
P
E
C
3
TMR
Logical Processor
P
E
A
2
P
E
B
2
P
E
C
2
Blade Element
(Slice)
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