hp workstations zx6000, hp server rx2600 - operation and maintenance guide

System Board
System Board Components
Appendix B
181
Intel® Itanium® 2 Processor
The Intel® Itanium® 2 processor provides the following features:
• 8-stage pipeline, general purpose ALU, two integer units, one floating-point unit
• L0 cache split instruction and data L0 caches:
— Instruction cache: 16k, 4-way associative
— Data cache: 16k, 4-way associative
— 64-byte line size
— 57.6 GB/sec read bandwidth at 900 MHz (28.8 GB/sec for floating-point double
precision)
• L1 unified cache
• L2 cache unified 256K 8-way associative cache:
— 3 MB, 12-way associative (1.5MB with 900MHz processor)
— 128-byte line size
— Virtual/Physical addressing 64-bit virtual address
— 50-bit physical address
Note that you may install up to two processors in your system.
Processor Bus
The Intel® Itanium® 2 processor bus (Front Side Bus, FSB) in this product is qualified
to run at 200 MHz. Data on the FSB are transferred at a double data rate, which allows
a peak FSB bandwidth of 6.4 GB/sec.
ZX1 I/O and Memory Controller
The ZX1 I/O and memory controller chip provides eight I/O ropes that support PCI,
PCI-X and/or AGP via this chip. This controller chip supports a direct data path between
I/O and main memory without crossing the processor bus. The peak I/O bandwidth is
4GB/second.
The ZX1 I/O and memory controller chip provides two memory cells, each consisting of
144-bit data buses. The DDR bus is transferred at a double data rate, which provides a
peak bandwidth of 8GB/sec at an extremely low latency (approximately 70nS for an idle
system, open page access).