hp workstations zx6000, hp server rx2600 - operation and maintenance guide

System Board
System Board Components
Appendix B
183
The ZX1 I/O and memory controller is partitioned into five major components:
Table B-1 Five Major Components of the ZX1 I/O and Memory
Controller
Bus Interface Bloc (BIB) This block provides the interface between the processor’s
bus and the memory controller (MC) and the I/O cache
controller (IOCC) blocks of this chip.
Memory Controller (MC) This block provides the interface between the main memory
and the bus interface block. This controller provides the
lowest idle system latency.
I/O Cache Controller (IOCC) This block is responsible for taking Direct Memory Access
request generated for the Rope-Quad Controller and issuing
them either to the process bus or directly to the memory
controller.
Rope-quad Controller (RQC) This block provides an interface between the IOCC and up
to four I/O ropes. The ropes it controls can be bundled as
single-wide, double-wide or quad-wide bundles. The
rope-quad controller provides the “pre-rope” functionality
such as error detection, prefetching, flushing and side-band
address decoding.
Clocking The clock for the BIB and the majority of the I/O blocks are
derived from the main processor bus clock. This is referred
to as the “blck” or the bus clock domain. Each of the I/O rope
interfaces have two independent clock domains, one for
outgoing data and one for incoming data. The source for the
outgoing clock domain is programmatically selected from
one of two clock sources. The expected rope frequencies are
266MHz, 200MHz, 133MHz and 100MHz. The two clocks
are internally generated by multiplying two separate
external clock sources by eight or sixteen to derive the
desired frequencies. The source for the incoming I/O clock
domain is the incoming “istrb” signal for that rope. The
“istrb” signal is allowed to be asynchronous relative to the
outgoing clock signal (ostrb).