HP Integrity rx3600 Server User Service Guide

14. Add the CPU board CRU and turn on system power. The cooling fans should turn on and stay
on.
If the installed CRUs are all functional, the system should initiate POST on all processors. It is
recommended that you view the system console output using live logs to ensure that POST is initiated
and completes successfully.
If POST does not start after a few seconds, there may be a CPU board or processor problem.
Typical problems show up in the SEL or FWP. If the IMPI event logs do not point to a root cause,
escalate to bring in expert assistance.
CPU, Memory and SBA
All of the CPU, memory controller, and System Bus Adapter (SBA or I/O rope controller) functions
reside on the processor board assembly FRU. Memory DIMMs reside on memory board FRUs. The
Local Bus Adapter (LBAs or PCI-X bus controller chips) reside on the common I/O backplane CRU
along with core and customer Host Bus Adapter (HBA device controller) I/O cards. This section
discusses the roles of logical CPUs, physical memory ranks, and the rope interfaces in the SBA
logic of the zx2 chip.
Troubleshooting the rx3600 CPU
Each rx3600 server supports one or two Intel Itanium processor modules. Each processor module
contains two individual CPU cores. This results in four physical CPUs when two processor modules
are installed in rx3600 servers.
Each physical CPU core contains logic to support two physical threads. This results in up to eight
physical threads, or the equivalent of 8 logical CPUs, when two processor modules are installed
and enabled in rx3600 servers. The operating system kernel attaches one or more software
processes to each available thread. In multiple processor servers, having more threads means all
software processes are launched and executed faster.)
Itanium Processor Load Order
For a minimally loaded server, one Itanium processor module must be installed in CPU socket 0
on the processor board CRU, and its threads must be enabled by user actions. You can install an
additional identical processor in CPU socket 1.
Processor Module Behaviors
All enabled CPUs and their threads become functional when the system powers on. Each thread
acquires instructions from the CPU instruction and data caches to complete early self tests and
rendezvous.
The CPU communicates with the PDH until memory is configured. After the memory is configured,
the CPUs communicate with memory.
Local machine check abort (MCA) events cause the physical CPU core and one or both of its logical
CPUs within that processor module to fail while all other physical CPUs and their logical threads
continue operating. Double-bit data cache errors in any physical CPU core cause a Global MCA
event that causes all logical threads and physical CPUs in the server to fail and reboot the operating
system.
142 Troubleshooting