User Service Guide, Fifth Edition - HP Integrity rx8640 SEU

Table 1-1 SEU Core I/O Boot Path (continued)
DescriptionPathDeviceCore I/O card
The SYS LAN connector located on core I/O 3.3/0/0/1/01 Gb LAN3
Hard drive located in the bottom left disk bay.3/0/0/2/0.6.0SCSI drive3
Removable media DVD (X = 2) or DDS-4 (X = 3) tape drive
located in the upper disk bay.
3/0/0/2/1.X.0SCSI drive3
Hard drive located in the bottom right disk bay.3/0/0/3/0.6.0SCSI drive3
SCSI drive connected to the external SCSI Ultra3 connector on
the core I/O card.
3/0/0/3/1SCSI drive3
PCI-X Backplane
The PCI-X board provides sixteen 64-bit, hot-swappable PCI-X slots. The application specific
integrated circuit (ASIC) on each cell board in the server chassis has SBA link connections to
communicate with one SBA controller. The ASIC in cell locations zero and one are connected to
the SBA ASICs on the PCI board installed in the main server chassis through the printed circuit
board routing. External E-link cables are used to connect the ASICs on cell boards residing in
locations two and three of the server to the two SBA ASICs on the PCI-X board in the SEU.
The SBA ASIC converts the SBA link protocol into ropes. Each SBA has 16 ropes that connect to
LBA ASICs. The LBA ASICs convert ropes protocol into PCI/PCI-X bus protocol. Each PCI/PCI-X
slot is connected to its own dedicated LBA. Of the 16 LBAs (one for each of the 16 slots), 14 LBAs
have dual ropes connected from an SBA. The remaining two LBAs have a single rope connected
from the SBA. Each of the 16 PCI/PCI-X slots is capable of 133 MHz PCI-X and 4 slots on each
Core I/O rope are capable of 266 MHz PCI-X. All 16 PCI/PCI-X slots on the PCI-X backplane are
keyed for 3.3 V connectors (accepting both Universal and 3.3 V cards). One rope from each of
the two SBA ASICs connects to an LBA ASIC on the Core I/O Backplane board. Each of these
two LBAs provides a PCI bus that connects to an associated core I/O board.
NOTE: There is one single rope PCI slot for each cell. Slots 0 and 8 have a single rope associated
with them so the bandwidth is one-half the bandwidth for PCI cards installed in slots 1–7. Priority
in installing PCI cards should be given to slots with double ropes since they have double the
bandwidth of a single rope slot. See Table 1-3 “Cell 3 PCI Slot Boot Paths” for details.
The PCI-X backplane contains an altimeter circuit. This circuit is used to adjust the chassis fan
speeds for the operating altitude at power on and during MP initialization. The chassis fans
consist of the two front fans, the two rear fans, and the six PCI-X I/O assembly fans. If an altimeter
failure is detected, the information is logged as an Event ID then propagated to the OS level to
be picked up by monitoring diagnostics.
The altimeter circuit is checked at power on by the MP. If an expected value is returned from
the altimeter circuit, the altimeter is determined good. The altimeter reading is then set in
non-volatile random access memory (NVRAM) on board the core I/O card. If the value is ever
lost like for a core I/O replacement, the NVRAM will be updated at next boot provided the
altimeter is functioning normally. If the altimeter has failed, and the stable storage value has
been lost because of a core I/O failure or replacement, the MP will adjust the fan speeds for sea
level operation.
18 Server Expansion Unit Overview