User Service Guide, Fifth Edition - HP Integrity rx8640 SEU

Figure 1-4 System Backplane (Side View in Chassis)
The voltage regulator modules (VRMs) that provide 3.3 V and 3.3 V standby are located on this
backplane. The backplane also has the connectors to provide a hardware interface to the SEU
chassis.
Clocks and Reset
The system backplane contains reset and clock circuitry that propagates through the whole
system. The system backplane central clocks drive all major chip set clocks.
Server Expansion Unit Interconnect
Manageability data will be transferred between the server chassis and the SEU through the main
E-link cables that tie cell boards in the server to SBA links in the SEU. This manageability link
enables ethernet protocol communications between the manageability processors in the server
and in the SEU.
PCI-X
The SEU supports two internal SBAs. The SBAs generate 32 rope buses (16 per SBA). The 32
available internal rope buses are divided in the following manner:
• Two ropes are routed as single rope bundles to support the core I/O boards through LBAs
located on the core I/O backplane.
• Two ropes are routed as single rope bundles to two LBAs to support two slots for PCI and
PCI-X cards.
• Twenty-eight ropes are bundled in two rope pairs to 14 LBAs to support 14 slots for PCI
and PCI-X cards.
The PCI-X backplane is the primary I/O interface for SEU systems. It provides 16 64-bit, hot-plug
PCI/PCI-X slots. Fourteen of the slots have dual ropes connected to the LBA chips. The remaining
two slots have a single rope connected to each LBA chip. Each of the 16 PCI/PCI-X slots is capable
of 133 MHz PCI-X and 4 slots on each Core I/O rope are capable of 266 MHz PCI-X. All 16 PCI
22 Server Expansion Unit Overview