HP StorageWorks U320e SCSI Host Bus Adapter user guide (AH627-96001, March 2007)

Glossary
ANSI American National Standards Institute
arbitrate Process of selecting one L_ Port from a collection of ports which ask for use of
the arbitrated loop at the same time.
Asynchronous
Information Pro-
tection
AIP: although most Ultra320 traffic is sent synchronously and protected by CRC,
some information i s still sent asynchronously. AI P implements CRC-level error
checking on asynchronous traffic ensuring end-to-end data integrity.
autone gotiation hardware senses and automatically responds depending on configuration
BER Bit Error Rate. A measure of transmission accuracy; the ratio of bits received in
error to bits sent.
bit Smallest unit of data a computer can process: a single binary digit with a
value of either 0 or 1.
bus a collection of unbroken signal lines used to transmit information from one part
of a computer system to another. Taps on the lines c onnect devices to the bus.
byte an ordered set of 8 bits
channel a point-to-point link which transports data from one point to another.
CPU Central Processing Unit. The por tion of the computer that performs computations.
CRC Cyclic Redundancy Checking, an error-correcting code which calculates a
numeric value for received and transmitted data. If no error has occurred
during transmission, the CRC for both received and transmitted data should
be the same.
destination ad-
dress
A value in the frame header of each frame which identifies the port in the node
where the frame is being sent
device driver A program that allows a m icroprocessor to direct the operation of a peripheral
device.
DMA Direct M emory Access. A way to move data from a storage device d irectly to
RAM without using the CPU's resources.
DMA bus master Allows a peripheral to control the flow of data to and from system memory by
block as opposed to allowing the processor to control the data by bytes (PIO
or programmed I/O).
domain validation Before sending data, domain validation verifies that the physical connection is
capable of hand ling the negotiated transfer speed. If the system determines that
Ultra320 speeds are not feasible, a slower speed is enforced.
double transition
cloc king
Increases the data line fre quency to equal that of the request signal, a llowing
sampling on both the leading and trailing edges of the request signal. Clocking
can be set to ensure compa tibility with legacy devices.
flow control The target indicates to the initiator when the last packet of a data stream will b e
transferre d so that the initiator can flush FIFOs and terminate pre-fetch sooner
than previously possible. B asically, the target warns the initiator that the transfer
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