Accelerator Manual Data Alignment Addendum

Accelerator Manual Data Alignment Addendum—524963-001

4-1

Misalignments in TNS and

Accelerated Modes

TNS compilers catch most violations of programming rules for their languages;

however, some coding errors, particularly misuses of pointers and addresses, can

produce erroneous TNS object code without compile-time or run-time warnings. When

erroneous TNS object code executes, its misbehavior depends on its execution

environment (TNS mode or accelerated mode, or execution on TNS CISC systems).

These execution environments are compatible for legal TNS object code, but they

sometimes handle erroneous TNS object code differently.

A common cause of erroneous TNS object code is a source program that uses odd-

byte addresses in contexts where the compiler expects even-byte (word-aligned)

operands. When the compiler applies a TNS word instruction to an operand with an

odd-byte address, run-time results are unpredictable. The instruction might do any, or

any combination, of the following:

•

“Round down” the misaligned address (as the TNS CISC processors always did)

•

Use the misaligned address without rounding it down

•

Cause the instruction to fail

The TNS instruction’s misalignment behavior depends on the following:

•

Operand size (16-bit, 32-bit, or 64-bit)

•

Execution mode

In TNS mode or accelerated mode, the action also depends on the following:

TNS opcodes such as QCMP

Although 64-bit integers with odd-byte addresses usually are not rounded

down, they can be—QCMP is one such example.

Contextual optimizations

How the instruction's result is used by later instructions

•

The SCF attribute TNSMISALIGN (see Section 3, Misalignment Handling)