Accelerator Manual Data Alignment Addendum

Accelerator Manual Data Alignment Addendum—524963-001
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1 Introduction
On TNS systems, a word is 16 bits. The TNS instruction set includes data access
instructions that use 32-bit byte addresses that must be even-byte aligned (that is,
aligned 0 modulo 2) for correct operation. This requirement remains even after the
Accelerator translates TNS code into RISC code. In TNS mode and accelerated mode,
addresses that are odd-byte aligned (that is, aligned 1 modulo 2) are called misaligned.
TNS processors consistently “round down” misaligned addresses (that is, they ignore
the low-order bit).
TNS/R processors handle the misaligned addresses of TNS programs inconsistently,
rounding down some but not others and behaving differently in TNS mode and
accelerated mode. These problems do not occur in programs that follow all of the
programming rules for TNS languages, but compilers cannot catch misaligned
addresses that are computed at run time.
The behavior of TNS programs with misaligned addresses on TNS/R processors is
almost impossible to predict. If you are not sure that your program has only aligned
addresses, you can use the tracing facility to detect whether programs are using
misaligned pointers, and if so, where. You should then change the programs to avoid
misalignment.
In addition to the Accelerator, the data misalignment issue might affect the following
HP compilers. If you use these compilers, see the appropriate data alignment
addenda:
Compiler T Number Addendum
TNS C T9255 C/C++ Programmer's Guide Data Alignment Addendum
TNS C++ T9541
TNS c89 T8629
TNS COBOL85 T9257 COBOL85 Manual Data Alignment Addendum
TNS/R pTAL T9248 pTAL Reference Manual Data Alignment Addendum
TNS TAL T9250 TAL Programmer's Guide Data Alignment Addendum