Accelerator Manual (G06.24+, H06.03+)

Preparing Your Program for TNS/R Systems
Accelerator Manual—527303-002
2-12
Shift Instructions With Dynamic Shift Counts
pointer P contains a byte address. When P is set to -1, the structure starts on an
odd-byte boundary; therefore, the program might trap or it might continue
executing.
STRUCT s(*);
BEGIN
INT i;
INT(32) d;
INT j;
END;
PROC test;
BEGIN
INT .EXT p(s);
@p:= -1d; ! "nil" 4-byte pointer to structure
p.d := %habcd1234%d; ! Results are unpredictable
END;
Shift Instructions With Dynamic Shift Counts
The implementation of TNS instructions for signed arithmetic and unsigned logical
shifts with dynamic shift counts differs between TNS and TNS/R systems. This
difference applies to both single-word (16-bit) and double-word (32-bit) shift
instructions.
For single-word shift operations with dynamic shift counts:
•
TNS/R systems accept counts within the range of 0 to 31. Shift counts of 16 to 31
are treated as 16. Shift counts greater than 31 give undefined results.
For double-word shift operations with dynamic shift counts:
•
TNS systems accept counts within the range of 0 to 255. Shift counts of 32 to 255
are treated as 32.
•
TNS/R systems accept counts within the range of 0 to 32,767. Shift counts greater
than 32 are treated as 32.
Dynamic shift counts that fall outside of the acceptable ranges give undefined results.
The ALS, LLS, ARS, and LRS instructions implement single-word shifts and the DALS,
DLLS, DARS, and DLRS instructions implement double-word shifts.
The TAL compiler generates these instructions for the bit-shift operators ('<<', '>>', <<,
and >>) if the operand to the right of the operators is not a constant. These instructions
can also be found in TAL CODE statements. Refer to the appropriate system
description manual for more information about the TNS instruction set. Refer to the
TAL Reference Manual for details on TAL bit-shift operators.