Accelerator Manual (G06.27+, H06.04+, J06.03+)

Introduction
Accelerator Manual—527303-003
1-5
Cross-Platform Acceleration
The inline code expansion factor measures the worst-case increase in main memory
required for accelerated code; the typical increase is less. It is the number of bytes of
RISC code divided by the number of bytes of TNS code. RISC instructions are 32 bits
and TNS instructions are 16 bits; thus, a one-to-one instruction matching produces an
inline expansion factor of 2. The Accelerator listing reports the inline code expansion
factor.
The typical inline expansion factor in executable RISC code compared to TNS code is
2 to 4 times. In one typical OLTP application, the code pages working set for the HP-
supplied system code increased approximately 190 percent on a TNS/R as compared
to a TNS system.
Cross-Platform Acceleration
The Accelerator is supported on H-series systems, enabling you to accelerate TNS
object files on the TNS/E platform for execution on the TNS/R platform. (A file with a
MIPS region only runs in interpreted mode only on the TNS/E platform). The TNS/E
Figure 1-4. Comparing TNS and Accelerated Object Files Sizes With a Symbols
Region
TNS Object Code
Binder Region
Symbols Region
Accelerated
Object Code
VST0103.vdd