COBOL Manual for TNS and TNS/R Programs

Glossary
HP COBOL Manual for TNS and TNS/R Programs—522555-006
Glossary-35
TNS/E architecture
TNS/E architecture. NonStop Series/Itanium architecture. HP computers that are based on
Itanium technology. TNS/E architecture implements the Itanium instruction set
[explicitly parallel instruction set computing (EPIC)] and are upwardly compatible with
the TNS and TNS/R system-level architectures.
TNS/E native compiler. A compiler in the TNS/E development environment that generates
TNS/E native object code, following the TNS/E native-mode conventions for memory,
stack, registers, and call linkage. The ECOBOL compiler is an example of such a
compiler. Contrast with TNS compiler and TNS/R native compiler.
TNS/E native mode. The primary execution environment on a TNS/E system, in which
native-compiled Intel® Itanium® object code executes, following TNS/E native-mode
compiler conventions for data locations, addressing, stack frames, registers, and call
linkage. Compare to TNS interpreted mode and TNS accelerated mode. See also
TNS/R native mode.
TNS/E native object code. The Intel® Itanium® instructions that result from processing
program source code with a TNS/E native compiler. TNS/E native object code
executes only on TNS/E systems, not on TNS systems or TNS/R systems.
TNS/E native object file. An object file created by a TNS/E native compiler that contains
Intel® Itanium® instructions and other information needed to construct the code
spaces and the initial data for a TNS/E native process.
TNS/E native process. A process initiated by executing a TNS/E native object file.
Compare to TNS process and TNS/R native process.
TNS/E native user library. A user library available to TNS/E native processes in both the
Guardian and Open System Services (OSS) environments. A TNS/E native user library
is implemented as a TNS/E native dynamic-link library (DLL).
TNS/R. Refers to fault-tolerant HP computers that support the HP NonStop™ operating
system and are based on 32-bit reduced instruction-set computing (RISC) technology.
TNS/R systems run the MIPS-1 RISC instruction set and can run TNS object files by
interpretation or after acceleration. TNS/R systems include all HP systems that use
NSR-x processors. Compare to TNS and TNS/E.
TNS/R architecture. NonStop Series/RISC architecture. HP computers that are based on
RISC technology. TNS/R architecture implements the RISC instruction set and are
upwardly compatible with the TNS system-level architecture.
TNS/R native compiler. A compiler in the TNS/R development environment that generates
TNS/R native object code, following the TNS/R native-mode conventions for memory,
stack, 32-bit registers, and call linkage. The NMCOBOL compiler is an example of
such a compiler. Contrast with TNS compiler and TNS/E native compiler.