Debug Manual

Debug Manual—421921-003
2-1
2
Using Debug on TNS/R Processors
When debugging on HP NonStop Series/RISC (TNS/R) processors in native mode,
Debug provides information about the RISC state of the process so that you can debug
at the RISC instruction level when necessary. Program execution in native mode
consists entirely of RISC instructions and TNS/R register use.
When debugging programs in TNS or accelerated mode, you do not need to know the
TNS/R architecture, except for some low-level debugging. You do, however, need to
understand the HP NonStop Series (TNS) environment. Debug provides TNS
breakpoints and information on the TNS environment registers.
For your convenience, this section provides an overview of information that you need
to debug programs at the RISC instruction level. This section discusses these topics:
•
TNS/R Memory Addressing on page 2-1
•
Execution Options on page 2-3
•
TNS and RISC Execution Correspondence (Accelerated Mode) on page 2-5
•
Breakpoints on page 2-5
•
TNS/R Registers on page 2-10
•
TNS and TNS/R Register Correspondence on page 2-12
For debugging at the RISC instruction level, you are assumed to be familiar with the
TNS/R machine architecture, which is described in the NonStop S-Series Server
Description Manual.
TNS/R Memory Addressing
TNS/R memory is accessible through Debug with 32-bit addresses. Memory
accessible while debugging in nonprivileged mode is:
•
User code space (0x70000000 through 0x71FFFFFF)
•
User library space (0x72000000 through 0x73FFFFFF)
While debugging in privileged mode, access to the system library space and system
code space are permitted. Address ranges for the different code areas are illustrated in
Figure 2-1 on page 2-2.
Hexadecimal is the default numeric base for 32-bit TNS/R addresses to be displayed
by Debug or entered as input in Debug statements.