Debug Manual

Table Of Contents
Using Debug on TNS/R Processors
Debug Manual421921-003
2-2
TNS/R Memory Addressing
Figure 2-1. Diagram of TNS/R Memory
Native User Code; TNS
or
Accelerated User Library
Native
System Code
UCr or UL
TNS Code
0x72000000 through 0x723FFFFF
0x72400000
0x72400000 + header-len
through 0x73FFFFFF
SL
TNS or Accelerated System
Library
TNS Code 0x7A000000 through 0x7A3FFFFF
0x7A400000
0x7A400000 + header-len
through 0x7BFFFFFF
SCr
SLr
ULr
SC
TNS or Accelerated
System Code
TNS Code 0x80000000 through 0x803FFFFF
0x80400000
0x80400000 + header-len
through 0x807FFFFF
Millicode
UCr or UC
TNS Code
Accelerator Header
Accelerated Code
0x70000000 through 0x703FFFFF
0x70400000
0x70400000 + header-len
through 0x71FFFFFF
Native, TNS, or Accelerated User
Code
0x72000000
0x 73FFFFF
F
0x7A000000
0x7BFFFFFF
0x7C000000
0x7DFFFFFF
0x74000000
0x79000000
0x80000000
0x7E000000
0x7FFFFFFF
0x807FFFFF
0x80800000
0x81FFFFF
0x70000000
0x 71FFFFF
F
Native
User Library
Native
System Library
Accelerator Header
Accelerated Code
Accelerator Header
Accelerated Code
Accelerator Header
Accelerated Code
SRL Space 0x74000000 through 0x79FFFFFF
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