Debug Manual

Table Of Contents
Using Debug on TNS/R Processors
Debug Manual421921-003
2-6
Setting TNS Breakpoints
instruction would be approximate. Also, multiple RISC breakpoints could map to a
single TNS instruction.
Breakpoint correspondence is illustrated in the following set of figures.
Setting TNS Breakpoints
Setting any allowable TNS breakpoint causes a corresponding breakpoint in the RISC
code. You set a TNS breakpoint by using a B command that includes a reference to a
TNS address (for example, a UC address). The PMAP command shows the allowable
TNS location with > or @ characters. How TNS breakpoints correspond to RISC
breakpoints is illustrated in Figure 2-2, which shows setting breakpoints in the user
code area.
Note. TNS breakpoints can be set only at memory-exact or register-exact points because a
corresponding RISC breakpoint can also be set. Some TNS breakpoints cannot be set at
other points because there is no corresponding RISC instruction, as illustrated in the figure
below with the double slash (//) symbol.
Figure 2-2. How TNS Breakpoints Can Correspond to RISC Breakpoints
B UC. n
+nnn
User Code Area for ProcA
B UC. n +nnn specifies a TNS breakpoint
Register-Exact Point
TNS Instructions RISC Instructions
Register-Exact PointB UC. n
+nnn
Memory-Exact Point
B UC. n
+nnn
//
//
Legend
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