Debug Manual

Using Debug on TNS/R Processors
Debug Manual—421921-003
2-7
Setting RISC Breakpoints
Setting RISC Breakpoints
A RISC breakpoint is allowed on any valid RISC address. A RISC breakpoint in
accelerated code does not cause a corresponding TNS breakpoint to be set even
though a corresponding TNS instruction might exist. You set a RISC breakpoint by
using a B command that includes the 32-bit address mode. How RISC breakpoints
correspond to TNS instructions is illustrated in Figure 2-3, which shows setting
breakpoints in the accelerated user code area.
Rules About RISC Breakpoints
These rules about breakpoints apply to accelerated programs:
•
A breakpoint set on a TNS instruction also sets a breakpoint in the generated RISC
instruction.
•
Whether a TNS or RISC breakpoint is actually accessed depends on whether a
process is executing in TNS or accelerated execution mode. A TNS breakpoint
occurs in TNS execution mode; a RISC breakpoint occurs in accelerated execution
mode.
Figure 2-3. How RISC Breakpoints Correspond to TNS Instructions
BN 0x70 nnnnnn
BN 0x70 nnnnnn
User Code Area for ProcA
BN 0x70 nnnnnn specifies a RISC breakpoint
Register-Exact Point
TNS Instructions
RISC Instructions
//
Register-Exact Point
Legend
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