Debug Manual
Table Of Contents
- What’s New in This Manual
- About This Manual
- 1 Introduction
- Execution Modes on TNS/R Systems
- What User Access Is Required for Debugging
- How to Make a Process Enter Debug
- How to Select Debug as the Debugger
- Why a Process Enters Debug
- How to Determine Process State on a Trap or Signal
- Ending a Debug Session
- What Appears in the Debug Header Message
- How to Use Debug
- How Debug Breakpoints Work
- 2 Using Debug on TNS/R Processors
- 3 Debug Command Overview
- 4 Debug Commands
- Command Summary
- A Command
- AMAP Command
- B Command
- BASE Command
- BM Command
- C Command
- CM Command
- D Command
- DJ Command
- DN Command
- EX[IT] Command
- F[ILES] Command
- FC Command
- FN Command
- FNL Command
- FREEZE Command
- HALT Command
- H[ELP] Command
- I Command
- IH Command (TNS/R Native and OSS Processes)
- INSPECT Command
- LMAP Command
- M Command
- MH Command (TNS/R Native and OSS Processes)
- P[AUSE] Command
- PMAP Command (Accelerated Programs)
- PRV Command
- R Command
- S[TOP] Command
- T Command
- V Command
- VQ Command
- VQA Command
- = Command
- ? Command
- A Error Messages
- B ASCII Character Set
- C Command Syntax Summary
- Register Syntax
- Expression Syntax
- Address Syntax
- A Command
- AMAP Command
- B Command
- BASE Command
- BM Command
- C Command
- CM Command
- D Command
- DJ Command
- DN Command
- EX[IT] Command
- F[ILES] Command
- FC Command
- FN Command
- FNL Command
- FREEZE Command
- HALT Command
- H[ELP] Command
- I Command
- IH Command
- INSPECT Command
- LMAP Command
- M Command
- MH Command
- Output-Device Syntax
- P[AUSE] Command
- PMAP Command
- PRV Command
- R Command
- S[TOP] Command
- T Command
- V Command
- VQ Command
- VQA Command
- = Command
- ? Command
- D Session Boundaries
- E Correspondence Between Debug and Inspect Commands
- F Sample Debug Sessions
- Glossary
- Index
Using Debug on TNS/R Processors
Debug Manual—421921-003
2-9
Considerations for Memory-Access Breakpoints
TNS Example
This code sequence will be used to show the results of the interaction between
memory-access breakpoints and code breakpoints, in TNS mode:
The following example shows the program hitting a memory-access breakpoint. The
displayed P address is one instruction address past the address of the instruction that
caused the memory-access breakpoint. The memory-access breakpoint was triggered
by the STOR instruction at %76.
The displayed $PC address is from the millicode used to emulate the TNS instructions.
The following example shows the results of having a code breakpoint on the instruction
that will cause the memory-access breakpoint. First the code breakpoint is reported;
the memory-access breakpoint is reported after resuming the program.
Native Example
This code sequence shows the results of the interaction between memory-access
breakpoints and code breakpoints, in native mode:
The following example shows the program hitting a memory-access breakpoint. The
displayed $PC address is one instruction address past the address of the instruction
050,03,00009-i %74,4
%000074: LADR L+004 LLS 01 STOR L+035 LDI +000
050,03,00009-bm l+35 , w
XA: 0x0000005E MAB: W (DATA SEG)
050,03,00009-r
DEBUG P=%000077, E=%000207, UC.%00-MEMORY ACCESS BREAKPOINT-
MEMORY ACCESS BREAKPOINT OCCURRED AT $PC=0x7E004A60
050,03,00014-bm l+35, w
XA: 0x0000005E MAB: W (DATA SEG)
050,03,00014-b %76
ADDR: UC.%00,%000076 INS: %044435 SEG: %020740
INS: STOR L+035
050,03,00014-r
DEBUG P=%000076, E=%000200, UC.%00-BREAKPOINT-
050,03,00014-r
DEBUG P=%000077, E=%000207, UC.%00-MEMORY ACCESS BREAKPOINT-
MEMORY ACCESS BREAKPOINT OCCURRED AT $PC=0x7E004A60
050,03,00270-i 0x70000438, #4
70000438: ADDIU t0,sp,128 SW t0,120(sp) ADDIU t1,gp,-32750
70000444: SW t1,176(sp)