Debug Manual

Using Debug on TNS/R Processors
Debug Manual—421921-003
2-10
TNS/R Registers
that caused the memory-access breakpoint. The memory-access breakpoint was
triggered by the store word (SW) instruction at 0x7000043C.
This example shows the results from putting a breakpoint on a code location that
causes a memory-access breakpoint:
Observe that the first $PC address ($PC=0x7FF00E20), after executing the second R
command in the above example, is outside the range of the program. But the second
displayed $PC address ($PC=0x7000043C) is the location of the instruction that
caused the memory-access breakpoint, not the location of the next instruction as
shown previously. This is the result of resuming the program from the code breakpoint.
TNS/R Registers
Debug displays the values of the TNS/R hardware registers. The TNS/R registers
include the 32 general-purpose registers $00 through $31, the arithmetic HI/LO
registers, the program counter $PC, and the IEEE floating-point registers.
The TNS/R registers are:
050,03,00270-bm $sp+#120, w
N: 0x4FFFFEA8 MAB: W
050,03,00270-r
DEBUG $PC=0x70000440 -MEMORY ACCESS BREAKPOINT-
MEMORY ACCESS BREAKPOINT OCCURRED AT $PC=0x70000440
050,03,00269-bm $SP + #120, w
N: 0x4FFFFEA8 MAB: W
050,03,00269-b 0x7000043c
N: 0x7000043C INS: 0xAFA80078
INS: SW t0,120(sp)
050,03,00269-r
DEBUG $PC=0x7000043C -RISC BREAKPOINT ($PC: 0x7000043C)-
050,03,00269-r
DEBUG $PC=0x7FF00E20 -MEMORY ACCESS BREAKPOINT-
MEMORY ACCESS BREAKPOINT OCCURRED AT $PC=0x7000043C
$00 Hard wired to the value 0
$01 through $31 General-purpose registers
$HI, $LO Arithmetic high and low registers
$PC TNS/R program counter
$F00 through
$F31
IEEE floating-point general purpose registers
$FCR31 IEEE floating-point status/control register