Debug Manual

Table Of Contents
Using Debug on TNS/R Processors
Debug Manual421921-003
2-13
TNS and TNS/R Register Correspondence
Table 2-2. TNS/R Register Use Summary (page 1 of 2)
Register Alias
Native
Execution
Mode TNS Execution Mode
Accelerated
Execution Mode
$00 Zero constant Zero constant Zero constant
$01 $AT Assembler
temporary
Temporary Temporary
$02, $03 $V0, $V1 Function values Temporary Temporary
$04..$07 $A0..$A3 Arguments Temporary Temporary
$08..$10 $T0..$T2 Temporary Temporary Temporary
$11 $T3 Temporary Rj_Ptr (executor
variable)
Temporary
$12 $T4 Temporary Arg (executor variable) Temporary
$13 $T5 Temporary Iword (executor
variable)
RA2 register
$14 $T6 Temporary K (carry bit) K (carry bit)
$15 $T7 Temporary CC (condition code; <0,
=0, >0)
CC (condition
code)
$16 $S0 Saved variables Do_Next R0
$17 $S1 Saved variables (spare) R1
$18 $S2 Saved variables Extended address in
read-only memory of
instruction decode
tables
R2
$19 $S3 Saved variables SG_Ptr. Extended
absolute address in
Kseg0 of system global
(SG) data segment
R3
$20 $S4 Saved variables RP wrap base (address
of R0)
R4
$21 $S5 Saved variables Cur_Cseg. Current
code segment as an
extended 32-bit address
(can be UC, UL, SC, or
SL)
R5
$22 $S6 Saved variables RPX. Extended
address pointing into
register stack array
holding TNS registers
R0 through R7
R6