Debug Manual

Using Debug on TNS/R Processors
Debug Manual—421921-003
2-15
TNS and TNS/R Register Correspondence
The bits and the decoding for the $FCR31 register are as follows:
Bit Meaning
<7> FS: 0 or 1 When the FS bit is set, denormalized results are flushed to 0.
<8> C: 0 or 1 The C bit is set to 1 if the condition is true, and the bit is cleared to
0 if the condition is false.
<14:19>: CAUSE The CAUSE bits reflect the results of the most recently executed
instruction. They identify the exceptions raised by the last
floating-point operation and raise an interrupt or exception if the
corresponding ENABLE bit is set. If more than one exception
occurs on a single instruction, each appropriate bit is set. Note that
the CAUSE bits are managed by the NonStop operating system,
the user code has no access to them.
<20:24>: ENABLE A floating-point exception is generated any time a CAUSE bit and
the corresponding ENABLE bit are set. A floating-point operation
that sets an enabled CAUSE bit forces an immediate exception.
<25:29>: FLAGS The FLAG bits are cumulative and indicate that an exception was
raised by an operation that was executed after the FLAG bits were
explicitly reset. The FLAG bits are set to 1 if an IEEE 754
exception is raised; otherwise, they remain unchanged. A bit in the
FLAG field is set only if the corresponding exception condition
occurs and the corresponding trap is disabled.
<30:31>: Round Mode These bits specify the rounding mode that the floating-point unit
(FPU) uses for all floating-point operations.