Inspect Manual

Using Inspect on a TNS/R System
Inspect Manual—429164-006
15-8
Pipeline Instruction Processing
performed while also ensuring that locations exist, usually at the beginning of
statements, where the TNS program state is consistent.
Example
This example illustrates how optimized code increases performance by utilizing
registers to reduce memory accesses.
The use of general purpose registers by the accelerator can have a number of effects
on debugging. It may change the memory reference patterns of the program, causing
some data breakpoints, particularly read breakpoints, not to be triggered. It also results
in locations at which displayed memory may not be accurate (if a more recent value is
stored in a register) and locations at which memory cannot be “safely” modified (a
more recent copy may be stored in registers).
Pipeline Instruction Processing
Like other RISC processors, TNS/R processors pipeline instruction execution, allowing
components of instructions to be decoded and executed in parallel. This allows the
execution of most instructions to complete in one cycle. The exceptions are load and
branch instructions, which require an additional cycle.
The effect that pipelining has on debugging is that it results in a four cycle delay before
data breakpoints are reported.
Optimizations With Loads
Load instructions load values from memory. On TNS/R processors, load instructions do
not complete in the single cycle required to complete most instructions.
Figure 15-2. Memory Access by Optimized vs. Non-Optimized Code
Statement #1: C=A+B
Statement #2: E=C+A
Non-Optimized Code
Optimized Code
Memory
DataRegs
DataRegs
#1 Load A
Load B
Add (A+B)C
Store C
#2 Load C
Load A
Add (C+A)E
Store E
A
B
C
E
A
B
C
C
A
E
A
B
C
E
#1 Load A
Load B
Add (A+B)C
Store C
#2 Add (C+A)E
Store E
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