NonStop S-Series Hardware Installation and FastPath Guide (G06.25+)

Glossary
HP NonStop S-Series Hardware Installation and FastPath Guide—529443-001
Glossary-116
TNS code segment identifier
routines. Each TNS code segment contains its own procedure entry-point (PEP) table
and external entry-point (XEP) table. It can also contain read-only data.
TNS code segment identifier. A seven-bit value in which the most significant two bits
encode a code space (user code, user library, system code, or system library) and the
five remaining bits encode a code segment index in the range 0 through 31.
TNS code segment index. A value in the range 0 through 31 that indexes a code segment
within the current user code, user library, system code, or system library space. This
value can be encoded in five bits.
TNS code space. One of four addressable collections of TNS object code in a TNS
process. They are User Code (UC), User Library (UL), System Code (SC), and System
Library (SL). UC and UL exist on a per-process basis. SC and SL exist on a per-node
basis.
TNS compiler. A compiler in the TNS development environment that generates 16-bit TNS
object code following the TNS conventions for memory, stacks, 16-bit registers, and
call linkage. The TNS C compiler is an example of such a compiler. Contrast with
TNS/R native compiler.
TNS emulation software. The set of tools, libraries, and system services for running TNS
object code on TNS/R systems. On a TNS/R system, the TNS emulation software
includes the TNS Object Code Interpreter (OCI), the Accelerator, and various millicode
libraries.
TNS fixup. A task performed at process startup time when executing a TNS object file. This
task involves building the procedure entry point (PEP) table and external entry point
(XEP) table and patching PCAL and XCAL instructions in a TNS object file before
loading the file into memory. See also TNS mode, procedure entry-point (PEP) table,
and external entry-point (XEP) table.
TNS instructions. Stack-oriented, 16-bit machine instructions that are directly executed on
TNS systems by hardware and microcode. TNS instructions can be emulated on
TNS/R systems by using millicode, an interpreter, and either translation or
acceleration. Contrast with MIPS RISC instructions.
TNS interpreted mode. A TNS emulation environment on a TNS/R system in which
individual TNS instructions in a TNS object file are directly executed by interpretation
rather than permanently translated into MIPS instructions. TNS interpreted mode runs
slower than TNS accelerated mode. Each TNS instruction is decoded each time it is
executed, and no optimizations between TNS instructions are possible. TNS
interpreted mode is used when a TNS object file has not been accelerated for that
hardware system, and it is also sometimes used for brief periods within accelerated
object files. Accelerated or interpreted TNS object code cannot be mixed with or called
by native mode object code. Contrast with TNS accelerated mode and TNS/R native
mode.