NonStop S-Series Server Description Manual (G06.24+)

Memory Addressing and Access

HP NonStop S-Series Server Description Manual—520331-003

4-32

Kseg1 Memory Access

The preceding topics in this section explain the concepts of virtual memory addressing.

This and the remaining topics in this section consider how physical memory is actually

accessed in the processor. Because access to memory through Kseg1 is the simplest,

it is described first, illustrated in Figure 4-15.

The memory caches are not used when memory is addressed through Kseg1. All such

memory references go directly to physical memory and are used for memory-mapped

hardware addressing. As shown by the numbered steps in the figure, the virtual

address from the processor is taken as the physical address (simply by stripping the

three most significant bits of the 32-bit address) and applied directly to the memory

hardware for access.

Although this mode of access is simple and direct, it does have negative

considerations. The first involves, of course, the reason why memory caches were

invented in the first place—to enhance performance for frequently accessed code and

data. For example, load instructions using uncached addressing require the instruction

processor to stall for many cycles until the data is ready.

Another negative consideration is the possibility of cache consistency problems,

wherein the same area of memory might be accessed both through the caches and

bypassing the caches.

Also, the processor accepts Kseg1 addresses only to access a properly-aligned 32-bit

word. Attempting a half-word (16-bit) or byte access via a Kseg1 address causes a

hardware-error freeze.

For these reasons, Kseg1 addressing is rarely used in NonStop servers.

The sequence for Figure 4-15 is as follows. (1) The RISC instruction processor applies

a virtual address to any of the four areas of process address space. (2) If the address

is for Kseg1, it is a physical address and is delivered directly to the memory control

logic on the memory boards. (3) The memory control logic accesses physical memory

to read or write data or to fetch instructions.