NonStop S-Series Server Description Manual (G06.24+)

Memory Addressing and Access
HP NonStop S-Series Server Description Manual—520331-003
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Kseg0 Memory Access
Kseg0 Memory Access
Kseg0 addressing is similar to Kseg1 addressing, providing access to exactly the same
physical memory. However, memory information is transferred between memory and
the memory caches in blocks and as individual four-byte words between the caches
and the instruction processor. Thus the access is not direct, as in the case of Kseg1
addressing.
There are two levels of caches, designated primary and secondary. Also, there are
two primary caches, one for instructions (read only) and one for data (read and write).
These are shown in Figure 4-16. The primary caches are comparatively small (16K
bytes); they are indexed with the virtual address. The single secondary cache is larger
(varies in size depending on processor model; typically a half megabyte, one
megabyte, or two megabytes); it is indexed with the physical address. For Kseg0
addresses, the physical address is derived by simply stripping high-order bits from the
virtual address.
In operation, the RISC instruction processor attempts to read an instruction from (or
read data from or write data to) the appropriate primary cache. To do so, it checks the
cache tags (physical address part of cache lines) to determine whether one line
contains the addressed location. If so, the data word or instruction is read from the
instruction or data cache (or is stored into the data cache through a store buffer in the
case of writing data). That is a primary cache hit.
If the content of the addressed location is not in the primary cache, the instruction
processor indexes into the secondary cache using the physical address. It checks the
lines contained in the cache for a secondary cache hit. If the line is present in the
secondary cache, it is transferred (filled) into the primary cache. Then the read or write
can take place with the primary cache.
However, if the content of the addressed location is not in the secondary cache, the
processor issues a command to main memory to read a block of data into the
secondary cache. At that point, the line is transferred to the primary cache and the
addressed information is transferred to or from the instruction processor, in accordance
with the original read or write request.
For any write operations, the data is written into cache, merging with the existing data,
and at some later time is written to main memory—“write-back” cache.
In summary the sequence is as follows. (1) The RISC instruction processor indexes
into the primary caches. (2) For a read, it reads the appropriate cache slot (expecting
data or instruction); for a write, it stores data in the data cache through the store buffer.
(3) If the data or instruction is in the cache, go to Step 8. (4) On a primary cache miss,
the processor indexes into the secondary cache. (5) Line-fill the primary cache. (6) In
case of a secondary cache hit, return to Step 2. (7) In case of a secondary cache
miss, the processor goes to memory to fill the cache line; return to Step 5. (8) The
processor uses the read data or sends write data to memory through the write buffer.