NonStop S-Series Server Description Manual (G06.24+)

Memory Addressing and Access
HP NonStop S-Series Server Description Manual—520331-003
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Kseg2 and Nonprivileged Space Memory Access
Kseg2 and Nonprivileged Space Memory
Access
For Kseg0 addressing (previous topic), the physical address needed for cache access
is derived simply by stripping high-order bits from the virtual address. For Kseg2 and
nonprivileged space addressing, virtual addresses must specifically be translated to
physical.
The RISC processor includes a special-purpose cache called the translation
lookaside buffer (TLB) to translate virtual addresses to physical addresses. The TLB
performs its translations for both forms of virtual address: relative (in the case of
nonprivileged space addresses) and absolute (in the case of Kseg2 addresses). The
unit of translation is the page; that is, virtual page numbers are translated to physical
page numbers (frames).
The TLB can contain only 96 page translations at a time (48 even-odd pairs).
Therefore, there is a backup structure in memory, consisting of page mapping tables
(detailed later) that are the ultimate source of translations used in the TLB.
In operation, as presented in Figure 4-17, the TLB is scanned (simultaneously and in
parallel with the indexing of the primary caches) for a matching virtual page address. A
successful match either must have the correct nonprivileged space number or the TLB
entry must be marked as “global.” If a match is found, the physical frame number
contained in that location of the TLB is the desired translation. That is a TLB hit. The
cache logic can continue its access, now having a verified physical address.
If no match is found, or if a match is found but the TLB entry is not marked as “valid,” a
TLB miss has occurred. A succession of translation tables in memory is accessed to
find the page location. If the page is in memory, its address is installed in the TLB (this
takes a few dozen machine cycles). Otherwise, this is a page fault; the desired virtual
page is on disk (or nonexistent). The current process gets suspended at this point until
the operating system has fetched that page into memory. Then, when that process
executes again, the instruction that received the page fault is tried again.
Most of the TLB slots are thus filled by the action of memory reference misses
randomly overwriting previous page translations. There is no checking for frequency of
reference or other factors for those slots. However, the first few slots of the TLB
(specifiable) are reserved by the millicode and are never overwritten.
The instruction translation lookaside buffer (ITLB) is a two-entry substructure that
permits instruction address translation to be done in parallel with data address
translation. It is filled from the TLB when there is an instruction address miss.
The sequence for Figure 4-17 is as follows. (1) The TLB and ITLB are scanned for a
matching virtual address, in parallel with cache indexing. (2) If TLB hit occurs, the
physical address is thus verified for cache-hit testing; see previous topic. (3) If TLB
miss occurs, translation tables are accessed in memory to compute the physical
address. (4) When the address is obtained, it is put in the TLB, and the operation
repeats Steps 1 and 2.