NonStop S-Series Server Description Manual (G06.24+)

Memory Addressing and Access

HP NonStop S-Series Server Description Manual—520331-003

4-42

Address Translation of Global Elements

As was shown in the first topic of this section, parts of the nonprivileged space and

most of the privileged space of virtual memory are global among the currently defined

processes. The entire range of virtual addresses constituting absolute virtual memory

(most of Kseg2), for example, is global to all process address spaces. Some parts of

nonprivileged space, such as the system library and RISC millicode regions, also need

to be global to all process address spaces.

In all such cases, no process identification (TLBPID) is needed. Instead, for any global

addresses entered in the TLB, the Global bit (bit 51) is set to 1. When the TLB is

scanned for matching virtual addresses, the TLB logic ignores the TLBPID field if the

Global bit is equal to 1. In that case, a translation hit occurs whenever the virtual page

number field of the TLB entry matches the 17 most significant bits of the virtual

address. (As mentioned in the previous topic, the 18th bit is an even-odd selector and

is ignored when scanning for a hit.)

Figure 4-20 illustrates address translation for a global address in either the

nonprivileged space or the Kseg2 space.

Although the RISC chips provide for 64-bit addressing, and consequently an alternate

TLB format, this capability is not used in the NonStop S-series processors.

The 17 most significant bits of any virtual address are compared with the virtual page

number field of the TLB entry. If these fields match, and if the Global bit is set to 1, a

translation hit is achieved. The TLBPID field of the TLB entry is ignored. The Global

bit is set to 1 for all absolute segment pages and any other pages that are shared

among all processes.