NonStop S-Series Server Description Manual (G06.24+)

TNS Execution Modes
HP NonStop S-Series Server Description Manual—520331-003
6-2
Execution Modes for TNS Compatibility
Execution Modes for TNS Compatibility
This topic describes the basic differences between the two execution modes that
provide TNS compatibility.
TNS mode means that the interpreter millicode (in resident memory) executes on
behalf of the process, interpreting TNS instructions from the object code in memory
during run time. The millicode updates process state information as if the process
were executing on a TNS processor. Accelerated mode means that the object code
of the process, translated and optimized prior to run time, is directly executed by the
RISC processor. The distinction is illustrated in Figure 6-1.
In the operating system environment, processes compete for execution based on
operating system rules. All processes that are not currently running preserve flags (in
their register-save area) that state whether that process was using TNS or accelerated
mode. When a process is dispatched into execution, the instruction processor reads
those flags and accordingly fetches instructions from either the millicode (TNS mode)
or the program file (accelerated mode). In either case, the RISC processor “sees” only
a stream of RISC instructions; there is no switching of hardware or data paths.
In TNS mode, the interpreter millicode reads instructions from a TNS code segment in
memory as if they were data, analyzes those instructions, then executes a stream of
RISC instructions that perform the appropriate operations and update the saved copies
of TNS registers. Thus the state of the process can be made available in the form of
emulated TNS registers, register stack, and data stack.
In accelerated mode, the TNS object code has been translated from TNS instructions
to RISC instructions, and both forms of the object code exist in the object code file.
This work is performed prior to run time by the Accelerator. “Acceleration” of object
code is accomplished in several ways. For example, because the translation work is
performed “offline,” the Accelerator is allowed to look ahead in the instruction stream
and avoid generating RISC instructions for side effects (like setting of condition codes)
that will not be used. Also, translation needs to be performed only once for any section
of code, whereas the millicode must reinterpret the instructions on each pass through
that section.
In accelerated mode, the TNS state is not always readily available. That is because
sequences of TNS instructions are translated into equivalent but optimized sequences
of RISC instructions that compute the same results directly in RISC registers and
memory. The TNS instructions are not translated one-by-one into identical
intermediate values. When necessary, however, the corresponding state of TNS
registers can be derived at certain well-defined points. For some complex TNS
instructions, the accelerated code directly invokes millicode procedures.
In the example shown in Figure 6-1, process A uses TNS mode. The TNS instructions
from its object code file are read and interpreted by the millicode. The millicode
executes on behalf of the process and maintains process state. Process B uses
accelerated mode. Prior to run time, the TNS instructions in its code file were
translated and optimized into an accelerated code file. RISC instructions from the
accelerated code execute directly.