NonStop S-Series Server Description Manual (G06.24+)

TNS Execution Modes
HP NonStop S-Series Server Description Manual—520331-003
6-74
Procedure Return in Accelerated Code
Procedure Return in Accelerated Code
Besides actual mode switches, as described in the preceding topic, there are other
times when an accelerated program needs access to TNS information. One important
example is the return from any procedure call. In this case, what is needed is the
address derived by the EXIT instruction from the stack marker, rather than the next
RISC instruction.
Because the memory stack has exactly the same layout and content as on TNS
processors, there is no room in the stack marker for a 32-bit RISC return address.
Accelerated EXIT and RSUB instructions therefore work only from 16-bit TNS return
addresses.
The basic TNS mechanism of a procedure call and return is shown in the left part of
Figure 6-40. A call instruction (PCAL in this example) saves its return address
(a TNS P value) in a stack marker and jumps to the entry point of the procedure (N in
this example). After the called procedure has run to completion, it executes an EXIT
instruction. The EXIT instruction uses the saved TNS P and ENV values in the stack
marker to return to the instruction following the calling instruction.
The RISC instruction set does not include equivalent instructions to perform these
complex operations. Thus the simple jump instructions must be supplemented by a
separate mechanism that accomplishes the functions of the TNS EXIT instruction. The
complete call and return sequence is shown in the right part of Figure 6-40, in five
steps. This is the RISC equivalent (accelerated code) of the TNS code shown to the
left.
The accelerated code executes a jump to the entry point of the called procedure
(Step 1). Then the stack marker is built on the TNS data stack. (In contrast to the TNS
mode sequence, the stack marker is built after jumping to the entry point.) At the
conclusion of the called procedure, the code executes a jump to the EXIT millicode
routine (Step 2). The EXIT millicode reads the TNS P value that was saved in the
stack marker (Step 3). This P value is the C-relative address of the next TNS
instruction to be executed following the PCAL. The saved Environment register (also
in the stack marker) provides the correct segment identification (space ID).
Now the EXIT millicode refers to the Pmap table for this TNS code segment and finds
the starting point of the RISC instructions for that next TNS instruction (Step 4). After
forming a complete address out of the information in the Pmap table, the EXIT
millicode performs a jump to the appropriate point in the RISC code (Step 5).
The Pmap table may indicate that the TNS return address is not a “register-exact point”
(see Pmap discussion in the next topic). In that case, the EXIT millicode jumps to the
TNS interpreter millicode to execute the next portion of the program in nonaccelerated
mode.
In summary, with reference to Figure 6-40: (1) The jump to procedure N in RISC code
is equivalent to the jump performed by PCAL. (2) The final action of procedure N is to
execute a jump to EXIT millicode. (3) The EXIT millicode fetches the TNS P value of