NonStop S-Series Server Description Manual (G06.24+)

TNS Execution Modes
HP NonStop S-Series Server Description Manual—520331-003
6-82
Maintaining TNS State Values
Maintaining TNS State Values
The 32 general-purpose registers used by the RISC processor are numbered $0
through $31. $0 is hardwired to contain the value 0 and so is not considered in usage
assignments. Many of the registers are used by millicode or accelerated code for
expression evaluation, parameter passing, and so on. Those that are used to maintain
TNS state information fall in the range $14 through $30, as shown in Figure 6-44.
Some registers are assigned differently depending on whether the current mode of
execution is to execute the interpreter millicode or to directly execute accelerated
object code. Registers $16 through $23 contain the TNS register stack values while in
accelerated mode but not in nonaccelerated mode. (In the latter case, R0 through R7
are maintained in memory, in the RP wrap page, as previously described.) The other
seven registers, which are assigned to maintaining TNS state (unshaded), are
assigned consistently in both modes.
The carry and condition code values, although normally accessed as fields of the ENV
register in the TNS environment, are each assigned to whole registers in TNS/R
processors, because of frequent updates. The Carry (K) register can have one of two
values: 0 (no carry) or 1 (carry). The Condition Code can have three kinds of values:
0 (equivalent to N=0 and Z=1), any positive value (equivalent to N=0 and Z=0), or any
negative value (equivalent to N=1 and Z=0).
In both modes, registers $24 and $25 contain the user code address and ENV register
fields. “User code segment” is a pointer to the base of the most recently used TNS
code segment in the user code (UC) region (relative segment 3). “ENV” reflects the
maintained state of the TNS Environment register in stack marker format, with bit
assignments as follows: instruction breakpoint bit (1), LS (4), privileged mode (5), DS
(6), CS (7), T (8), overflow (10), and current space ID (11 through 15).
In TNS mode only, $20 through $24 contain the following values (all are 32-bit byte
addresses). “RP wrap base” is the address of the RP wrap page. “Current code
segment” is the address of the base of the current TNS code segment (relative
segment 2). “RP address” is the address of the current top-of-stack register; this
address is offset a multiple of 512 bytes from the RP wrap base. PX is the current
TNS program counter value, the address of the next TNS instruction to be interpreted;
because this address is a full 32-bit virtual address, decoding is needed to break it
down into a 16-bit word address, a segment number, and a region number (identifying
UC, UL, SC, or SL).
In accelerated mode, $16 through $23 contain relevant register stack values for R0
through R7. The RISC processor does not use these registers the same way as TNS
processors use the register stack. While they nominally represent TNS registers R0
through R7, they contain right-justified values consistent with TNS values only at
certain times.
In both modes, $28 contains the Pmap midpoint address for the current TNS code
segment. (The register contains 0 if the current segment is not accelerated.) As
described in the previous Pmap discussion, this address provides the basis for
converting between TNS P and RISC P values. $29 and $30 contain extended (32-bit