NonStop S-Series Server Description Manual (G06.24+)

Interrupt System
HP NonStop S-Series Server Description Manual—520331-003
8-4
Interrupt Sequence
Interrupt Sequence
Figure 8-2 expands on the simplified interrupt sequence shown in the preceding topic.
This diagram separates hardware and millicode elements (top part) from the software
elements (lower part).
The focal point for the various categories of interrupts is the Cause register in the RISC
chip. The shaded part of the Cause register represents “internal interrupts,” and the
unshaded part is used for “external interrupts.” The sequence is as follows.
When the processor millicode detects an interrupt condition from system code (1), or if
it detects a processing error, it records that information in a simulated interrupt register
(INTA) for later access by the interrupt handlers and sets a bit in the RISC Cause
register (2), if that bit is not already set.
On the other hand, if the interrupt condition comes from the ServerNet hardware, the
access validation and translation (AVT) hardware first puts an interrupt packet into
one of four dedicated interrupt queues (3). The queues are for IPC (interprocessor
communications) interrupts, I/O interrupts, error interrupts from either IPC or I/O, and
ServerNet coherency interrupts. When such interrupt packets are put into a queue, the
AVT sets a bit in an associated Cause register, which in turn sets one of the external
interrupt bits in the RISC Cause register (4).
The interrupt bit in the RISC Cause register causes an exception to occur, which
causes the processor to transfer control to the exception-handling millicode (5). The
exception-handling millicode either fully handles the interrupt itself (such as for
coherency) or it passes control to software. For software processing of interrupts, the
millicode fetches the appropriate entry from the system interrupt vector (SIV) (6), and
saves the environment of the interrupted code in a stack marker in the register-save
area (7). Using information from the SIV entry, the millicode transfers control to the
appropriate software interrupt handler (8).
In the case of ServerNet interrupts, an additional step is necessary, in which ServerNet
services picks out interrupt packets from the interrupt queues (9). An interrupt routine
that is part of ServerNet services maintains read pointers into the four queues, which
try to catch up to the write pointers maintained by the AVT as it puts more interrupt
packets into the queues. That is, the interrupt routine tries to empty the queues by
reading and servicing the interrupt packets as fast as the AVT can add more entries.
Reading and writing of the queues are done circularly.
The ServerNet services interrupt routine passes the information in each interrupt
packet to one of three interrupt handlers (10), as indicated. When the interrupt handler
finishes, it returns to ServerNet services (11).
Once the interrupt handler (or ServerNet services interrupt routine) completes
execution, it restores the environment of the interrupted code from the register-save
area (12) and returns to the interrupted code (13).