NonStop S-Series Server Description Manual (G06.24+)

Interrupt System

HP NonStop S-Series Server Description Manual—520331-003

8-6

Interrupt Stack Marker Format

Beginning with the G05.00 RVU, all code is native, and therefore the process

environment is saved in the register-save area. Figure 8-3 illustrates the arrangement

for storing the environment only for the case of TNS code.

The interrupt stack frames are allocated in the system data segment, each one

corresponding to one of the interrupt handlers. When an interrupt occurs, the

interrupted environment is saved in the stack marker of the appropriate stack frame.

The particular stack frame for a given type of interrupt is addressed by the LX register

(a RISC general-purpose register that contains a 32-bit byte address). The address

resides in the system interrupt vector and is referred to as LXi, where “LX” is the byte

address of the first L location in the system data segment and “i” is the interrupt

number (an index).

The interrupt stack marker provides sufficient space to store both the RISC

environment and the TNS environment of the code that was currently executing.

Although the stack marker has a fixed format, individual slots might not be filled in all

situations. Only the information actually needed to restore the preinterrupt state is

actually stored.

The RISC environment consists of the 31 general-purpose registers (GPR 0 always

contains the value 0 and so never needs to be saved), plus the arithmetic high and low

registers, two program counter values, the current mode (accelerated or

nonaccelerated), and other information. Of the two program counter values, one is the

address at which the interrupt occurred (or the address that caused the interrupt); the

other is the address where execution of the process (or other interrupt handler) is

normally expected to resume. (These values are often identical.)

In addition to storage space for RISC state, the stack marker also provides

14 TNS-word entries for TNS information. These entries are allocated in the same

sequence as in CISC TNS processors, but four entries (space ID, S, P, and L) are

never used. Only the Mask and Environment register values are saved—and they are

always saved whenever the mode is accelerated or TNS. Of the Environment register

bits, only PRIV and DS (bits 5 and 6) are ever saved. Conversely, the register stack

values (R0 through R7) are saved only in nonaccelerated mode.

The SX register is set to contain the 32-bit byte address of the final location of the

stack marker, which is the top of the interrupt stack when the interrupt handler begins

execution.