NonStop S-Series Server Description Manual (G06.24+)

Interrupt System
HP NonStop S-Series Server Description Manual—520331-003
8-8
Transferring Control to an Interrupt Handler
Transferring Control to an Interrupt Handler
After the interrupted environment has been saved, as described in the preceding topic,
the interrupt millicode transfers control to the interrupt handler in system software. To
do this transfer, the millicode refers to a table of 32-byte items in system data called
the system interrupt vector (SIV) and selects the appropriate entry. See Figure 8-4.
To start the interrupt handler, the following steps occur, all involving SIV fields.
1. The E value of the SIV entry is loaded into the Environment register. E defines the
interrupt handler’s environment. Typically it contains a hexadecimal value of 705
or 706: that is, privileged, system code, system data, and system code segment
number 5 or 6.
2. LXi is loaded into the RISC general-purpose register that is used as L. LXi is
configured to contain the byte address of the “base” of the interrupt stack for this
particular interrupt. Specifically, it points at the (unused) L value location in the
stack marker (see preceding topic).
3. SX is set to LX + 16 bytes (that is, eight TNS words higher than LX).
4. The RISC program counter is set with the address PXi. PXi is the accelerated
code starting address of the interrupt handler.
5. The Mi value in the SIV entry is ANDed with the current Mask A register setting to
derive a new setting for the Mask A register. Mi is a mask value for masking off
unwanted interrupts while the handler for this particular interrupt executes.
The SIV entry also contains two fields that are needed for special purposes:
•
Pmap contains the byte address that points to the midpoint of the Pmap for the
TNS code segment containing the interrupt handler. The Pmap information is
needed for returning to the correct address whenever the interrupt handler calls
procedures or subprocedures.
•
The next two words are for passing parameters to the interrupt handler. The low-
order 16 bits in each word usually contain the 16-bit parameter that would be
passed to the interrupt handler in any TNS processor, and the high-order 16 bits, if
used, contain additional special parameter information.
At this point, the first instruction of the interrupt handler executes. The interrupt
handler runs to completion unless the interrupt handler’s current mask allows certain
interrupts and those interrupts do occur.
Finally, the interrupt handler executes an IXA (interrupt exit) instruction sequence,
which restores the interrupted environment saved in the interrupt stack marker. That
is, all registers, state values, and the program counter are returned to their preinterrupt
values. Also, the register stack (if it was necessary to save it) is restored.
After the IXA instruction sequence finishes, the restored version of the Mask A register
determines the next action. If no interrupt is pending, process execution (or some
other interrupt handler, or the idle process) resumes at the point of interruption. If