NonStop S-Series Server Description Manual (G06.24+)

Interrupt System
HP NonStop S-Series Server Description Manual—520331-003
8-12
TNS Interrupts
TNS Interrupts
The following paragraphs describe the TNS interrupts in order of their SIV numbers.
Each type requires zero, one, or two parameters. Table 8-1 on page 8-14 summarizes
the interrupts.
Uncorrectable
Memory Error (1)
This interrupt occurs when a memory word is accessed by the
processor and contains an error that cannot be corrected. Two
parameter words are placed in the SIV entry. The first
parameter word contains the physical address of the page at
fault. The second parameter word identifies the type of access
(data or instruction) and provides the syndrome bits generated
by the error correction circuitry. The syndrome bits provide
information for service providers.
Memory Access
Breakpoint (2)
This interrupt occurs when the memory breakpoint has been
armed by the SMBP instruction and the breakpoint memory
address has been accessed in the desired manner. There is no
parameter. No interrupt occurs if the breakpoint was armed by
the service processor (SP); in this case, the processor performs
a system freeze and enters the halt loop. This interrupt
operates with less spatial precision and timing precision than on
TNS processors.
Instruction Failure
(3)
This interrupt occurs when an unimplemented instruction is
executed, or when execution of a privileged instruction is
attempted by a program that is not in privileged mode, or when
an abnormal condition is detected during the execution of other
instructions. The first parameter is not used. The second
parameter contains a trap code that distinguishes among the
various kinds of instruction failures, and an indication of how the
error was detected.
Page Fault (4) This interrupt occurs when an attempt is made to access an
absent memory page (that is, its page table entry “valid” bit is
set to 0). The first parameter word is the absolute byte address
of the absent page.
Power Fail (8) This interrupt occurs when a processor power failure is
detected. The interrupt handler provides an orderly shutdown
sequence that executes before power drops to an inoperative
level. There is no parameter.
Correctable
Memory Error (9)
This interrupt occurs when a memory error occurred and can be
corrected. The parameter words are of the same form as those
for an uncorrectable memory error.