NonStop S-Series Server Description Manual (G06.24+)

Input/Output Operations
HP NonStop S-Series Server Description Manual—520331-003
10-16
Storage Write Request Processing
Storage Write Request Processing
When an I/O process in a processor requests a write to a storage device, the only
action that the processor initiates is to send the command to the controller. Thereafter,
it is the responsibility of the controller to transfer the data, pulling the data to itself as if
the controller is the originator of the request. The resultant sequence consists of three
phases, illustrated in Figure 10-8.
In the request phase, the module driver first of all assigns the data buffer a ServerNet
address and makes an entry in the access validation and translation table (AVTT).
Then the I/O process (1) builds a command descriptor block (CDB) and (2) embeds the
CDB in a command entry (CE). The CE includes addresses of the client buffers of the
data that the controller will pull later. Then the I/O process, through the XIO kernel,
calls the module driver to create and send a ServerNet packet to a certain ServerNet
addressable controller (3). The header of the created packet contains the destination
and source ServerNet IDs, and the address field contains the ServerNet address of the
next available slot in the appropriate global request buffer in the ServerNet adapter.
The module driver forwards the packet to ServerNet services, which transmits the
packet to the ServerNet adapter (4), through the hardware of the block transfer engine
(BTE) as a ServerNet write request. The ServerNet bus interface (SBI) returns a
simple response packet back to the BTE and writes the packet data (the CE) into the
addressed global request queue.
When the controller polls its global request queues, it finds the new request and
transfers it to its local request queue (5). At this point, the controller discovers that the
CDB it has received is requesting a write transfer (6).
In the data transfer phase, the controller initiates multiple read transactions (1) and
forwards each read request packet to the ServerNet bus interface (SBI) for
transmission through the ServerNet hardware to the access validation and translation
(AVT) logic in the processor (2).
For each received packet, the AVT logic validates the supplied ServerNet address,
translates that address to a physical address, and retrieves the requested data by
DMA transfers, up to 64 bytes each time, from the client’s data buffer (3). The AVT
packages the data into ServerNet read response packets and transmits the packets
back to the SBI (4).
The SBI supplies the packet data to the controller (5) to complete the read
transactions. The controller thereafter commands the storage I/O device to write the
data from the received packets (6).
At the end of the data transfer, the controller initiates the interrupt phase. The
controller creates an interrupt packet that it issues to the SBI as a ServerNet write
request (1). For this packet, the controller uses a specific ServerNet address in
processor memory that the module driver has allocated as an interrupt location. The
AVT in the processor receives this packet (2) and puts it into an interrupt queue (3).
When the interrupt is serviced, the I/O process is notified that the transfer has been
completed.