NonStop S-Series Server Description Manual (G06.24+)

TNS Instruction Set
HP NonStop S-Series Server Description Manual—520331-003
11-18
Definitions of TNS Instructions
source byte address, and C to contain a destination byte address. The source and
destination segments to be used are specified by the “S” and “D” fields of the
instruction and by the DS, CS, and LS, bits of the ENV register. If the source address
is specified as current code segment, the byte address is taken to be in the same 64K
half of the code space as the current P register value. If the source address is
specified as latest user code segment, the byte address is taken to be in the lower
64K-byte half of that segment. The “RL” field determines whether the source and
destination addresses will be incremented (“RL” = 0) or decremented (“RL” = 1) after
each comparison. The “RP” field is the value to which RP will be set upon instruction
termination. The instruction fetches the contents of source and destination addresses,
compares them, increments or decrements the addresses by 1 according to the “RL”
field, and decrements the byte count in A until either A = 0 or a noncomparison is
reached. If termination is due to a noncomparison, either CCG indicates that the byte
at C is greater than the byte at B, or CCL indicates that the byte at C is less than the
byte at B; A indicates the number of bytes left to compare. If termination is due to the
count running out, CCE indicates that all bytes compared exactly, and C and B will
point to the next locations not compared. For binary coding details, refer to Table B-3
on page B-3. Figure 11-7 on page 11-9 provides a comparison of ascending and
descending directions.
COMW (0262--). Compare Words. This instruction compares one area of memory
with another, a word at a time, until a noncomparison occurs or until a specified
number of comparisons have been made. The words being compared are treated as
unsigned quantities. COMW expects A to contain a word count, B to contain a source
word address, and C to contain a destination word address. The source and
destination segments to be used are specified by the “S” and “D” fields of the
instruction and by the DS, CS, and LS, bits of the ENV register. The “RL” field
determines whether the source and destination addresses will be incremented (“RL” =
0) or decremented (“RL” = 1) after each comparison. The “RP” field is the value to
which RP will be set upon instruction termination. The instruction fetches the contents
of source and destination addresses, compares them, increments or decrements the
addresses by 1 according to the “RL” field, and decrements the word count in A until
either A = 0 or a noncomparison is reached. If termination is due to a noncomparison,
CC indicates the results of the compare; CCE indicates that A has gone to zero. For
binary coding details, refer to Table B-3 on page B-3. Figure 11-7 on page 11-9
provides a comparison of ascending and descending directions.
CQA (000260). Convert Quad to ASCII. The absolute value of the binary-coded
quadrupleword integer in FEDC is converted to a string of ASCII-coded digits (decimal
base), and the resulting string is stored in the memory space defined by a starting byte
address in B and a byte count in A. If the conversion results in a truncation of leading
digits, overflow is set. Condition Code is set on the original value.
CQD (000247). Convert Quad to Double. The four-word value in DCBA is converted
to a doubleword by extracting the least significant two words. DCBA is deleted, and
the doubleword result is pushed onto the stack. Overflow is set if the operand was
greater than 2
31
–1 or less than –2
31
.